Abstract: Disclosed herein is a multi-channel device for detecting plasma at an ultra-fast speed, including: a first antenna module connected to a first output terminal in contact with a substrate on a chuck of a process chamber and extending to ground, and receiving a first leakage current leaking through the substrate to increase reception sensitivity of the leakage current; a first current detection module detecting the first leakage current; a current measurement module receiving the first leakage current output from the first current detection module, and extracting the received first leakage current for each predetermined period to generate a first leakage current measurement information; and a control module comparing the first leakage current measurement information with a reference value to generate first arcing occurrence information.

Abstract: A secondary battery includes an electrode assembly having a positive electrode provided with a positive electrode tab, a separator, and a negative electrode provided with a negative electrode tab, the positive electrode, the separator, and the negative electrode being wound, the electrode assembly having a core part at a center thereof; a can configured to receive the electrode assembly therein, the negative electrode tab being connected to the can; a cap assembly coupled to an opening of the can, the positive electrode tab being connected to the cap assembly; and a reinforcing member provided on an end of the separator exposed beyond the positive electrode or the negative electrode to prevent heat of the positive electrode tab or the negative electrode tab from being transferred to the separator.

Abstract: A battery mounting structure for a vehicle is provided to include a case having a first internal member that is disposed to be spaced parallel to an upper side of a lower panel of the case and a second internal member that is disposed perpendicular to the first internal member, and configured to accommodate a plurality of battery modules therein using the first internal member and the second internal member. An outer side member is provided in a shape protruding toward the outside on an outer side of the case. The battery modules are disposed in a stacking direction of battery cells that is parallel to a longitudinal direction of the first internal member.

Abstract: A proactively protected (P2) processing system and method is invented for stopping the cyber-attacks from malicious usages of computing systems. The invention is applicable to eliminate the roots of the cyber-threats before a successful cyber-incident. Thereby, demand for resilient computing systems to survive a cyber-incident will be disappeared. Any recovery act and information loss is not happened. The invention dynamically switches a plurality of instruction sets at random or scheduled time for determining authorized operations with code compatibility. Therefore, a P2 processing system and method can detect and delete only unauthorized operations before being executed while executing authorized operations.

Abstract: A method and system of the branch look-ahead (BLA) instruction disassembling, assembling, and delivering are designed for improving speed of branch prediction and instruction fetch of microprocessor systems by reducing the amount of clock cycles required to deliver branch instructions to a branch predictor located inside the microprocessors. The invention is also designed for reducing run-length of the instructions found between branch instructions by disassembling the instructions in a basic block as a BLA instruction and a single or plurality of non-BLA instructions from the software/assembly program. The invention is also designed for dynamically reassembling the BLA and the non-BLA instructions and delivering them to a single or plurality of microprocessors in a compatible sequence. In particular, the reassembled instructions are concurrently delivered to a single or plurality of microprocessors in a timely and precise manner while providing compatibility of the software/assembly program.

Abstract: A method and system of the branch look-ahead (BLA) instruction disassembling, assembling, and delivering are designed for improving speed of branch prediction and instruction fetch of microprocessor systems by reducing the amount of clock cycles required to deliver branch instructions to a branch predictor located inside the microprocessors. The invention is also designed for reducing run-length of the instructions found between branch instructions by disassembling the instructions in a basic block as a BLA instruction and a single or plurality of non-BLA instructions from the software/assembly program. The invention is also designed for dynamically reassembling the BLA and the non-BLA instructions and delivering them to a single or plurality of microprocessors in a compatible sequence. In particular, the reassembled instructions are concurrently delivered to a single or plurality of microprocessors in a timely and precise manner while providing compatibility of the software/assembly program.

Abstract: A compiler-assisted lookahead (CAL) memory system for a CAL microprocessor consisting of a CAL memory management unit, a CAL lookahead instruction (LI) and compatible instruction (CI) memory system, and a CAL LI and CI cache system, is designed for operating with a CAL frontend processor to fetch LIs and CIs in a lookahead manner and to reorder the LIs/CIs fetched before decoding them for producing compatible results of the program. The invention is for enhancing performance and energy-efficiency of loop operations by reusing the LIs and CIs in the loops without fetching them iteratively from the CAL memory system.

Abstract: A lookahead out-of-order instruction fetch (i-fetch) mechanism using separated control flow is invented for a microprocessor system. An application or compiled code is compiled to separate control-flow subprogram and functional subprogram containing blocks of contiguous instructions before runtime. The fetch mechanism fetches flow-control instructions from the separated control-flow subprogram first and then fetches the other contiguous instructions from the functional subprogram in series or in parallel. The lookahead out-of-order i-fetch mechanism is viable for high-bandwidth accurate fetch by out-of-order and parallel fetching the flow-control and the other instructions of each basic block via the separated paths.

Abstract: A method and system of the look-ahead branch prediction and instruction fetch are designed for hiding multi-cycle taken-branch prediction latency while providing accurate and timely instruction fetch and performing look-ahead branch prediction. The invention is designed for identifying the branches that require to be predicted and for reordering the branches in program to perform the look-ahead branch prediction operations during the invented compilation. The invention is also designed for delivering the branch look-ahead instructions comprising predictable branch instructions and the other instructions. In particular, the reordered branch look-ahead instructions are sequentially or concurrently fetched to a single or plurality of branch look-ahead microprocessors in an accurate and timely manner while dynamically recovering order of the branch look-ahead instructions to achieve compatibility of the original program.

Abstract: A compiler-assisted lookahead (CAL) memory system for a CAL microprocessor consisting of a CAL memory management unit, a CAL lookahead instruction (LI) and compatible instruction (CI) memory system, and a CAL LI and CI cache system, is designed for operating with a CAL frontend processor to fetch LIs and CIs in a lookahead manner and to reorder the LIs/CIs fetched before decoding them for producing compatible results of the program. The invention is for enhancing performance and energy-efficiency of loop operations by reusing the LIs and CIs in the loops without fetching them iteratively from the CAL memory system.

Abstract: A method and system of the look-ahead branch prediction and instruction fetch are designed for hiding multi-cycle taken-branch prediction latency while providing accurate and timely instruction fetch and performing look-ahead branch prediction. The invention is designed for identifying the branches that require to be predicted and for reordering the branches in program to perform the look-ahead branch prediction operations during the invented compilation. The invention is also designed for delivering the branch look-ahead instructions comprising predictable branch instructions and the other instructions. In particular, the reordered branch look-ahead instructions are sequentially or concurrently fetched to a single or plurality of branch look-ahead microprocessors in an accurate and timely manner while dynamically recovering order of the branch look-ahead instructions to achieve compatibility of the original program.

Abstract: A method and system of the compiler-assisted look-ahead instruction-fetch branch-prediction (CLIB) comprising simple, small, and twice as fast instruction caches are designed for improving both speed and accuracy of instruction fetch and branch prediction by prefetching and fetching a type of instructions for accurate, look-ahead instruction prefetching, fetching and branch prediction and another type of instructions for compatible instruction prefetch and fetch. The invention is also designed for converting each basic block found in the program compiled by compilers in prior arts to a look-ahead instruction and a single or plurality of compatible instructions. The invention is also designed for delivering the look-ahead instructions to branch predictors before fetching the compatible instructions of the look-ahead instructions.

Abstract: A method and system of the branch look-ahead (BLA) instruction disassembling, assembling, and delivering are designed for improving speed of branch prediction and instruction fetch of microprocessor systems by reducing the amount of clock cycles required to deliver branch instructions to a branch predictor located inside the microprocessors. The invention is also designed for reducing run-length of the instructions found between branch instructions by disassembling the instructions in a basic block as a BLA instruction and a single or plurality of non-BLA instructions from the software/assembly program. The invention is also designed for dynamically reassembling the BLA and the non-BLA instructions and delivering them to a single or plurality of microprocessors in a compatible sequence. In particular, the reassembled instructions are concurrently delivered to a single or plurality of microprocessors in a timely and precise manner while providing compatibility of the software/assembly program.

Abstract: A method and system of prefetching and fetching processor instructions is designed for reduced code fraction, for scaled packed instructions before runtime, and for adaptive, concurrent instruction prefetch and fetch at runtime. The invention is designed for reducing energy consumption of the instruction cache memories by accurately accessing the instructions that will be executed and by terminating instruction prefetch after prefetching instructions from the possible paths. The invention is also designed for improving performance by reducing branch instructions and by prefetching and fetching instructions adaptively. In particular, compiled native instructions are converted to mixed packed nonnative and non-packed native instructions for generating more streamlined code and storing the native instructions of the packed instructions in dedicated, separate regions of distinct addresses in the concurrent accessible instruction cache and main memories.

Abstract: A method and system of the instruction packing and scaling are designed for simultaneously enhancing energy efficiency by concurrent and advanced prefetching/fetching instructions via the small and/or banked caches and for improving the performance of microprocessors by reducing the fraction of program and by employing the simple and fast caches. The invention is also designed for converting high fraction code to simplified, branch-reduced, and hidden code during compilation time, for storing packed/scaled code to concurrently accessible the plurality of caches and main memories, and for reverting the code to the native instructions during the instruction prefetch and fetch operations. Consequently, the invention does not forward many flow control instructions including procedure callers/returns and unconditional branches to microprocessors.

Abstract: A method and system of the instruction packing and scaling are designed for simultaneously enhancing energy efficiency by concurrent and advanced prefetching/fetching instructions via the small and/or banked caches and for improving the performance of microprocessors by reducing the fraction of program and by employing the simple and fast caches. The invention is also designed for converting high fraction code to simplified, branch-reduced, and hidden code during compilation time, for storing packed/scaled code to concurrently accessible the plurality of caches and main memories, and for reverting the code to the native instructions during the instruction prefetch and fetch operations. Consequently, the invention does not forward many flow control instructions including procedure callers/returns and unconditional branches to microprocessors.

Abstract: Multiple instructions including branch instructions are grouped into a condensed variable length instruction. A trimmed and grouped branch instruction branches to one of the instructions in the same group. Therefore, a grouped instruction including branch(es) inherently executes correct branch behaviors without deploying any branch prediction schemes. In addition, a grouped instruction in a condensed form delivers multiple operations to execute without fetching all of the instructions grouped separately from the instruction memory via its caches while conserving instruction memory and/or cache as well as decreasing the number of bit switching on the bus. Software developers can make their own compatible, compact and ciphered instruction sets after grouping existing instructions in their software compiled with existing software compilers and the associated microprocessors.

Abstract: According to one embodiment, an instruction decoder for a computer processor includes a fixed instruction decoding portion and at least one look up table having a plurality of random access memory elements. The fixed instruction decoding portion has an input for receiving program instructions and an output coupled to a back-end processing engine. The instruction decoder is selectively operable to alternatively decode program instructions associated with a differing instruction set architectures by storage of logical values in the at least one look up table. Decoding of program instructions from one particular instruction set architecture are accomplished using the same logic gates as program instructions form other instruction set architectures.