Patents by Inventor Yong-Lack Choi
Yong-Lack Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8765572Abstract: A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.Type: GrantFiled: June 24, 2011Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-lack Choi, Chang-hyun Cho, Seung-pil Chung, Hyun-seok Jang, Du-heon Song, Jung-dal Choi
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Patent number: 8368138Abstract: Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.Type: GrantFiled: September 17, 2010Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Lack Choi, Sunghoi Hur, Jaeduk Lee, Jungdal Choi
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Patent number: 8183613Abstract: A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.Type: GrantFiled: January 6, 2010Date of Patent: May 22, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon Jeong, Yong-Chul Oh, Sung-In Hong, Sung-Hwan Kim, Yong-Lack Choi, Ho-Ju Song
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Publication number: 20110318914Abstract: A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.Type: ApplicationFiled: June 24, 2011Publication date: December 29, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-lack Choi, Chang-hyun Cho, Seung-pil Chung, Hyun-seok Jang, Du-heon Song, Jung-dal Choi
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Publication number: 20110073930Abstract: Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.Type: ApplicationFiled: September 17, 2010Publication date: March 31, 2011Inventors: Yong-Lack CHOI, Sunghoi HUR, Jaeduk LEE, Jungdal CHOI
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Patent number: 7816228Abstract: In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An insulation layer liner is formed on sidewalls of the isolation trench in the first region and the second region. An isolation layer fills an inner portion of the isolation trench. The insulation layer liner is partially removed to expose an upper surface of the substrate in the gate region of the first region, and an upper surface and sidewalls of the substrate in the gate region of the second region. A gate oxide layer and a gate electrode are formed on the exposed substrate.Type: GrantFiled: July 2, 2007Date of Patent: October 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hwan Kim, Chang-Woo Oh, Yong-Lack Choi, Na-Young Kim
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Patent number: 7799629Abstract: A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.Type: GrantFiled: April 9, 2009Date of Patent: September 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Na-Young Kim, Chang-Woo Oh, Sung-Hwan Kim, Yong-Lack Choi
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Publication number: 20100176451Abstract: A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.Type: ApplicationFiled: January 6, 2010Publication date: July 15, 2010Inventors: Hoon Jeong, Yong-Chul Oh, Sung-In Hong, Sung-Hwan Kim, Yong-Lack Choi, Ho-Ju Song
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Publication number: 20090203178Abstract: A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.Type: ApplicationFiled: April 9, 2009Publication date: August 13, 2009Inventors: Na-Young Kim, Chang-Woo Oh, Sung-Hwan Kim, Yong-Lack Choi
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Patent number: 7535051Abstract: A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.Type: GrantFiled: January 12, 2007Date of Patent: May 19, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Na-Young Kim, Chang-Woo Oh, Sung-Hwan Kim, Yong-Lack Choi
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Publication number: 20080124893Abstract: In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An insulation layer liner is formed on sidewalls of the isolation trench in the first region and the second region. An isolation layer fills an inner portion of the isolation trench. The insulation layer liner is partially removed to expose an upper surface of the substrate in the gate region of the first region, and an upper surface and sidewalls of the substrate in the gate region of the second region. A gate oxide layer and a gate electrode are formed on the exposed substrate.Type: ApplicationFiled: July 2, 2007Publication date: May 29, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Hwan Kim, Chang-Woo Oh, Yong-Lack Choi, Na-Young Kim
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Publication number: 20080096351Abstract: A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.Type: ApplicationFiled: January 12, 2007Publication date: April 24, 2008Inventors: Na-Young Kim, Chang-Woo Oh, Sung-Hwan Kim, Yong-Lack Choi
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Publication number: 20070048938Abstract: A method of manufacturing a MOS transistor with a multiple channel structure prevents damage to and loss of material of a channel region. The method includes: forming a stacked structure including a plurality of first material layers and a plurality of second material layers that have different etching selectivities and are alternately stacked on a semiconductor substrate; forming an active mask on a portion of the stacked structure, the active mask defining an active region; etching regions of the stacked structure to expose sidewalls of the stacked structure; forming a plurality of tunnels by selectively removing the first material layer between the exposed sidewalls of the stacked structure; removing the active mask; and forming a gate electrode on the active region to fill the plurality of tunnels.Type: ApplicationFiled: May 10, 2006Publication date: March 1, 2007Inventors: Eun-jung Yun, Sung-young Lee, Min-sang Kim, Sung-min Kim, Yong-lack Choi