Patents by Inventor Yong Li Xu

Yong Li Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11958789
    Abstract: A method for determining a consistency coefficient of a power-law cement grout includes: determining a water-cement ratio of the power-law cement grout; according to engineering practice requirements, determining a time required to determine the consistency coefficient of the power-law cement grout; and obtaining the consistency coefficient of the power-law cement grout. The method is accurate and reliable, requires less calculation, etc.; and has very high practical value and popularization value in environmental protection and ecological restoration.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: April 16, 2024
    Assignee: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Zhi-quan Yang, Jun-fan Xiong, Ying-yan Zhu, Yi Yang, Yong-shun Han, Muhammad Asif Khan, Jian-bin Xie, Tian-bing Xiang, Bi-hua Zhang, Han-hua Xu, Jie Zhang, Shen-zhang Liu, Qi-jun Jia, Cheng-yin Ye, Gang Li
  • Patent number: 9583425
    Abstract: A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 ?m) and fifty micrometers (50 ?m) from the lead. In some embodiments, the core covers between at least approximately one-third (?) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 28, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Yong Li Xu, Tiao Zhou, Xiansong Chen, Kaysar M. Rahim, Viren Khandekar, Yi-Sheng Anthony Sun, Arkadii V. Samoilov
  • Publication number: 20140131859
    Abstract: A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 ?m) and fifty micrometers (50 ?m) from the lead. In some embodiments, the core covers between at least approximately one-third (?) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.
    Type: Application
    Filed: June 28, 2013
    Publication date: May 15, 2014
    Inventors: Yong Li Xu, Tiao Zhou, Xiansong Chen, Kaysar M. Rahim, Viren Khandekar, Yi-Sheng Anthony Sun, Arkadii V. Samoilov
  • Patent number: 8575493
    Abstract: Semiconductor devices are described that have an extended under ball metallization configured to mitigate dielectric layer cracking due to stress, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests, or cyclic bending tests, and so on. In an implementation, the semiconductor package devices include an integrated circuit chip having a solder ball and under ball metallization, formed on the integrated circuit chip, which is configured to receive the solder ball so that the solder ball and the under ball metallization have a contact area there between, wherein the area of the under ball metallization is area greater than the contact area.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 5, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Yong Li Xu, Duane Thomas Wilcoxen, Yi-Sheng Sun, Viren Khandekar, Arkadii Samoilov
  • Patent number: 8084871
    Abstract: An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: December 27, 2011
    Assignee: Maxim Integrated Products, Inc.
    Inventors: S. Kaysar Rahim, Tiao Zhou, Arkadii Samoilov, Viren Khandekar, Yong Li Xu
  • Patent number: 7989961
    Abstract: An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 2, 2011
    Assignee: Maxim Integrated Products, Inc.
    Inventors: S. Kaysar Rahim, Tiao Zhou, Arkadii Samoilov, Viren Khandekar, Yong Li Xu
  • Publication number: 20110108981
    Abstract: An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.
    Type: Application
    Filed: November 10, 2009
    Publication date: May 12, 2011
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: KAYSAR RAHIM, TIAO ZHOU, ARKADII SAMOILOV, VIREN KHANDEKAR, YONG LI XU
  • Patent number: 7382059
    Abstract: In one embodiment, a semiconductor package is formed by adding a layer of particles to desired portions of a packing substrate. The layer of particles forms a matrix of crevices that provides a micro-lock feature for mechanically locking or engaging encapsulating materials.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: June 3, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Harold G. Anderson, Cang Ngo, Yong Li Xu, James Mohr