Patents by Inventor Yong Lin

Yong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154255
    Abstract: A battery connection module is provided. The battery connection module is adapted to connect a plurality of batteries, the battery connection module includes a plurality of busbars and a single layer wiring flexible circuit board. The plurality of busbars are used to connect a plurality of batteries in series. The single layer wiring flexible circuit board has multiple connector connecting points positioned to a front end portion thereof and a multiple traces, front ends of the multiple traces are respectively connected to the multiple connector connecting points, and rear end connecting points of some of the multiple traces are electrically and mechanically connected to the plurality of busbars, the multiple traces includes at least one rounding trace and at least one rounded trace, the rounding trace rounds the rear end connecting point of the rounded trace so as to round from one side of the at least one rounded trace to the other side of the at least one rounded trace.
    Type: Application
    Filed: January 15, 2024
    Publication date: May 9, 2024
    Inventors: Yong Lin, Shang-Xiu Zeng, Kian-Heng Lim, Yun-Jin Li
  • Patent number: 11979989
    Abstract: The present disclosure relates to a battery connection module and a battery device. The battery connection module includes a carrying tray, a plurality of busbars and a flexible circuit board. The plurality of busbars are provided to the carrying tray.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: May 7, 2024
    Assignee: Molex, LLC
    Inventors: Yong Lin, Shang Xiu Zeng, Kian Heng Lim
  • Publication number: 20240143145
    Abstract: A method and apparatus for aiming at a virtual object in a virtual environment, which: displays a user interface (UI), the UI including a picture of a virtual environment including a first virtual object and at least one second virtual object located in the virtual environment; displays a dot aiming indicator in the virtual environment in response to an aiming instruction, the dot aiming indicator being used for indicating an aiming point selected by an aiming operation on a ground plane of the virtual environment; and controls the first virtual object to aim at a target virtual object, which is a virtual object selected from a second virtual object in a target selection range which is a selection range determined by using the aiming point as a benchmark.
    Type: Application
    Filed: December 28, 2023
    Publication date: May 2, 2024
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yu Lin WAN, Jianmiao Weng, Xun Hu, Shan Dong Su, Yong Zhang
  • Publication number: 20240145719
    Abstract: A binder solution for an all-solid-state battery, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same, and more particularly to a binder solution for an all-solid-state battery, in which a polymer binder configured such that a non-polar functional group is bonded to the end of a polar functional group is used, whereby the polar functional group is provided by a deprotection mechanism of the polymer binder through a thermal treatment, thus increasing adhesion between electrode materials to thereby improve battery capacity and enabling a wet process to thereby reduce manufacturing costs, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Applicants: HYUNDAI MOTOR COMPANY, Kia Corporation, Seoul National University R&DB Foundation
    Inventors: Sang Mo Kim, Sang Heon Lee, Yong Sub Yoon, Jae Min Lim, Ju Yeong Seong, Jin Soo Kim, Jang Wook Choi, Kyu Lin Lee, Ji Eun Lee
  • Patent number: 11972557
    Abstract: Provided are a vibration object monitoring method and apparatus, a computer device, and a storage medium. The method includes: in response to detecting that a vibration object exists in a monitoring video picture for a target monitoring region, a vibration object region in the monitoring video picture is determined, where the vibration object region is a region where the vibration object is located in the monitoring video picture; displacement information of a key point of the vibration object in the vibration object region is recorded; vibration information of the vibration object in the monitoring video picture is determined based on the displacement information; and a vibration object monitoring result for the target monitoring region is generated according to the vibration information. The abnormal vibration monitoring can be performed on the vibration object in the target monitoring region in time according to this method.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: April 30, 2024
    Assignee: CSG POWER GENERATION CO., LTD.
    Inventors: Yumin Peng, Zhiqiang Wang, Hao Zhang, Hengjun Chen, Xun Hu, Tuixiang Feng, Liqun Sun, Man Chen, Yong Lu, Tao Liu, Kai Lin, Yulin Han
  • Patent number: 11973010
    Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 30, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hao-Lin Yen, Heng-Chi Huang, Yong-Zhong Hu
  • Patent number: 11955960
    Abstract: The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: April 9, 2024
    Assignee: CHIP-GAN POWER SEMICONDUCTOR CORPORATION
    Inventors: Ke-Horng Chen, Tzu-Hsien Yang, Yong-Hwa Wen, Kuo-Lin Cheng
  • Patent number: 11950412
    Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 2, 2024
    Assignee: Longitude Flash Memory Solutions LTD.
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
  • Patent number: 11942358
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11942053
    Abstract: Disclosed are a display panel and a driving method therefor, and a display device. Two adjacent rows of sub-pixels are taken as a row group, and the row group is provided with a first sub row group and a second sub row group that are arranged in a column direction; a gate electrode of a first transistor in the first sub row group is electrically connected to a first gate line; a gate electrode of a second transistor in the second sub row group is electrically connected to a second gate line; two adjacent sub-pixels in the column direction share one third transistor, and a gate electrode of the third transistor in the row group is electrically connected to a third gate line; and the first transistor and the second transistor in one column of sub-pixels are electrically connected to a data line by means of the shared third transistor.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 26, 2024
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xianglei Qin, Jian Lin, Yong Zhang, Limin Zhang, Zepeng Sun, Zhichao Yang, Liangzhen Tang, Zhilong Duan, Honggui Jin, Yashuai An, Lingfang Nie, Jian Wang, Li Tian, Jing Pang, Xuechao Song
  • Publication number: 20240087799
    Abstract: An inductor device including a frame portion, a first winding set, a second winding set and a first common magnetic core I piece is provided. The first winding set, the second winding set and the first common magnetic core I piece are disposed in the frame portion. The first common magnetic core I piece substantially connects the first winding set and the second winding set and the frame portion. The material of the two winding sets is different from that of the first common magnetic core I piece.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 14, 2024
    Inventors: Kai-De CHEN, Yong-Long SYU, Chen CHEN, De-Jia LU, Chao-Lin CHUNG
  • Patent number: 11927844
    Abstract: Provided is a display substrate. The display substrate includes: a base substrate including a display region and a non-display region surrounding the display region; a gate drive circuit disposed in the non-display region; a plurality of first signal lines disposed in the peripheral region and connected to the gate drive circuit; and a plurality of second signal lines disposed in the non-display region and connected to the gate drive circuit; wherein each of the first signal line and the second signal line is configured to supply a signal to the gate drive circuit, and a frequency of the signal supplied by the first signal line is lower than a frequency of the signal supplied by the second signal line.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: March 12, 2024
    Assignees: Beijing BOE Optoelectronics Technology Co., Ltd., BOE Technology Groups Co., Ltd.
    Inventors: Zepeng Sun, Yong Zhang, Xianglei Qin, Jian Wang, Yanchen Li, Jian Lin, Limin Zhang, Zhichao Yang, Liangzhen Tang, Zhilong Duan, Yashuai An, Lingfang Nie, Honggui Jin, Li Tian
  • Publication number: 20240078969
    Abstract: An image processing circuit includes a receiver, at least one memory, a recognition circuit, a calculation circuit and a compensation circuit. The receiver is configured to receive a current image frame and a plurality of previous image frames. The at least one memory is configured to store the plurality of previous image frames. The recognition circuit is configured to select a first previous image frame or a second previous image frame among the plurality of previous image frames from the at least one memory. The calculation circuit is configured to calculate a compensation value for the current image frame according to at least one of the first previous image frame and the second previous image frame by referring to a lookup table (LUT). The compensation circuit is configured to modify a current image data of the current image frame by using the compensation value.
    Type: Application
    Filed: August 21, 2023
    Publication date: March 7, 2024
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Xuan-Yong Lin, Shang-Yu Su, Feng-Ting Pai
  • Publication number: 20240072790
    Abstract: The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: KE-HORNG CHEN, TZU-HSIEN YANG, YONG-HWA WEN, KUO-LIN CHENG
  • Patent number: 11888179
    Abstract: A battery connection module includes a carrying tray, a plurality of busbars and a flexible circuit board. The plurality of busbars are provided on the carrying tray. The flexible circuit board is provided on the carrying tray, the plurality of busbars is adjacent to the flexible circuit board, and the busbar has a notch which is formed to a side toward the flexible circuit board and a notch side plate portion which is positioned alongside the notch, the flexible circuit board has a bending arm which integrally extend out from the flexible circuit board, the bending arm is positioned in the notch of the busbar and a tip of the bending arm is electrically connected to the busbar. In some embodiments, a battery connection module further includes an output connection port provided to the carrying tray. In some embodiments, a battery connection module further includes a connector provided to the carrying tray.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: January 30, 2024
    Assignee: Molex, LLC
    Inventors: Sheau Noan Cheong, Han Guan Tan, Yong Lin, Yun-Jin Li
  • Patent number: 11882637
    Abstract: An operation method of a proximity sensor comprises: controlling a light-emitting element by a processing circuit. Such control includes a plurality of light source on and light source off operations. An optical sensor receives light and outputs a sensing signal corresponding to the intensity of the light. The processing circuit computes the sensing signal to produce a sensing result. The plurality of light source on and light source off operations includes a group having two light sources on operations and two light sources off operations. The two light sources on operations in the group or the two light sources off operations in the group are performed consecutively. In this way, the ambient light components of the light source on and off operations may cancel out each other to reduce the ambient light components contained in the sensing results.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: January 23, 2024
    Assignee: Sensortek Technology Corp.
    Inventors: Meng-Yong Lin, Ming-Huang Liu, Jer-Hau Hsu, Cheng-Feng Liu
  • Patent number: 11876248
    Abstract: A battery connection module is provided. The battery connection module is adapted to connect a plurality of batteries, the battery connection module includes a plurality of busbars and a single layer wiring flexible circuit board. The plurality of busbars are used to connect a plurality of batteries in series. The single layer wiring flexible circuit board has multiple connector connecting points positioned to a front end portion thereof and a multiple traces, front ends of the multiple traces are respectively connected to the multiple connector connecting points, and rear end connecting points of some of the multiple traces are electrically and mechanically connected to the plurality of busbars, the multiple traces includes at least one rounding trace and at least one rounded trace, the rounding trace rounds the rear end connecting point of the rounded trace so as to round from one side of the at least one rounded trace to the other side of the at least one rounded trace.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: January 16, 2024
    Assignee: Molex, LLC
    Inventors: Yong Lin, Shang-Xiu Zeng, Kian-Heng Lim, Yun-Jin Li
  • Publication number: 20230399410
    Abstract: The present disclosure relates to the use of an anti-IL6 receptor antibody, or an antigen-binding fragment thereof, for treating polymyalgia rheumatica (PMR).
    Type: Application
    Filed: April 5, 2023
    Publication date: December 14, 2023
    Inventors: Jennifer SLOANE LAZAR, Yong LIN, Wanling WONG, Ying LIU, Frédéric MARRACHE, Kerri FORD, Stefano FIORE, Lita ARAUJO, Danielle ISAMAN, Jeffrey CURTIS, Chad NIVENS, Bola AKINLADE, Angeliki GIANNELOU
  • Publication number: 20230380768
    Abstract: Gastric resident electronics, devices, systems, and related methods are generally provided. Some embodiments comprise administering (e.g., orally) an (electronic) resident structure to a subject (e.g., a patient) such that the (electronic) resident structure is retained at a location internal to the subject for a particular amount of time (e.g., at least about 24 hours) before exiting said location internal to the subject. In some embodiments, the resident structure is a gastric resident electronic. That is to say, in some embodiments, the resident structure is configured for relatively long gastric residence and comprises an electronic component. In some embodiments, the structures and components described herein may comprise one or more components configured for the delivery of an active substance(s) (e.g., a pharmaceutical agent) to the subject.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 30, 2023
    Applicants: Massachusetts Institute of Technology, The Brigham and Women's Hospital, Inc.
    Inventors: Robert S. Langer, Carlo Giovanni Traverso, Yong Lin Kong
  • Patent number: D1020135
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 26, 2024
    Assignee: TANY TECHNOLOGY CO., LTD.
    Inventor: Yong Lin