Abstract: A method, apparatus, and scheduling system for managing a mix of time-critical messages and general messages. Messages, which are referenced by message identifiers stored in a transmission queue buffer, are scheduled for transmission using a schedule configuration table. The schedule configuration table defines an order for processing a mix of time-critical messages and general messages. The messages are scheduled according to the characteristics for time-critical messages and general messages defined in columns of configuration tables and status tables. The messages that have been scheduled are transmitted from an end system in which the time-critical messages are prioritized during transmission over the general messages.

Abstract: A method, apparatus, and scheduling system for managing a mix of time-critical messages and general messages. Messages, which are referenced by message identifiers stored in a transmission queue buffer, are scheduled for transmission using a schedule configuration table. The schedule configuration table defines an order for processing a mix of time-critical messages and general messages. The messages are scheduled according to the characteristics for time-critical messages and general messages defined in columns of configuration tables and status tables. The messages that have been scheduled are transmitted from an end system in which the time-critical messages are prioritized during transmission over the general messages.

Abstract: A first processing core selects a first memory address of a first memory area based on a last written buffer that identifies a last written memory address. The first memory area is a portion of a shared memory, and the first processing core has sole write access to the first memory area among a plurality of processing cores that use the shared memory. Data is written to the first memory address of the first memory area. After writing the data to the first memory address, the last written buffer is updated to designate the first memory address as the last written memory address of the first memory area. A second processing core of the plurality of processing cores is operable to access the data by accessing the last written buffer and determining, based on the last written buffer, that the data is stored at the first memory address.