Patents by Inventor Yong Loo Neo
Yong Loo Neo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6987031Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: August 27, 2002Date of Patent: January 17, 2006Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Patent number: 6964881Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: August 27, 2002Date of Patent: November 15, 2005Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Patent number: 6958537Abstract: A semiconductor device package is disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: August 4, 2004Date of Patent: October 25, 2005Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Publication number: 20050116337Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: January 3, 2005Publication date: June 2, 2005Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Patent number: 6825553Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: September 5, 2003Date of Patent: November 30, 2004Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Publication number: 20040229400Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: June 22, 2004Publication date: November 18, 2004Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Publication number: 20040084741Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.Type: ApplicationFiled: October 23, 2003Publication date: May 6, 2004Inventors: Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo, Swee Kwang Chua, Siu Waf Low
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Publication number: 20040046250Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: September 5, 2003Publication date: March 11, 2004Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Publication number: 20040042190Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package includes The package may include a variety of semiconductor dice thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements are also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: ApplicationFiled: August 27, 2002Publication date: March 4, 2004Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Shuangwu Huang
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Publication number: 20040043533Abstract: The present invention defines a packaging implementation providing a multi-chip multi-layer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate. Additional redistribution and interconnect layers above the multi-chip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment the cavities receive the dice with the active surface of the dice facing up wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the dice.Type: ApplicationFiled: August 27, 2002Publication date: March 4, 2004Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Publication number: 20040041221Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.Type: ApplicationFiled: August 28, 2002Publication date: March 4, 2004Inventors: Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo, Swee Kwang Chua, Siu Waf Low
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Publication number: 20030232488Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.Type: ApplicationFiled: August 28, 2002Publication date: December 18, 2003Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo
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Publication number: 20030227079Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.Type: ApplicationFiled: June 11, 2002Publication date: December 11, 2003Applicant: Micron Technology, Inc.Inventors: Yong Poo Chia, Suan Jeung Boon, Siu Waf Low, Yong Loo Neo, Bok Leng Ser