Abstract: A memory card includes a card substrate on which a controller and a memory device are mounted, and a card enclosure that accommodates the card substrate and exposes terminals for electrical connection to an external device. The controller is operable in a universal flash storage (UFS) mode and in a first sub-mode other than the UFS mode. The terminals that are exposed include a UFS terminal group according to a UFS standard, and a first sub-mode terminal group. The UFS terminal group includes first row terminals arranged adjacent to an insertion side edge of the memory card and second row terminals arranged apart from the insertion side edge such that the first row terminals are provided between the second row terminals and the insertion side edge. The first sub-mode terminal group is adjacent to the first row terminals.

Abstract: A memory card includes a card substrate on which a controller and a memory device are mounted, and a card enclosure that accommodates the card substrate and exposes terminals for electrical connection to an external device. The controller is operable in a universal flash storage (UFS) mode and in a first sub-mode other than the UFS mode. The terminals that are exposed include a UFS terminal group according to a UFS standard, and a first sub-mode terminal group. The UFS terminal group includes first row terminals arranged adjacent to an insertion side edge of the memory card and second row terminals arranged apart from the insertion side edge such that the first row terminals are provided between the second row terminals and the insertion side edge. The first sub-mode terminal group is adjacent to the first row terminals.

Abstract: A memory card includes a card substrate on which a controller and a memory device are mounted, and a card enclosure that accommodates the card substrate and exposes terminals capable of being electrically connected to an external device, wherein the controller is operable in a universal flash storage (UFS) mode and in a first sub-mode other than the UFS mode.

Abstract: A memory card includes a card substrate on which a controller and a memory device are mounted, and a card enclosure that accommodates the card substrate and exposes terminals capable of being electrically connected to an external device, wherein the controller is operable in a universal flash storage (UFS) mode and in a first sub-mode other than the UFS mode.

Abstract: A memory card adaptor is provided herein. The memory card adaptor may include a housing having a slot configured to accommodate a memory card. The memory card may include a signal terminal and non-signal terminals. For example, the signal terminal may be a high-speed and/or data transfer terminal, and the non-signal terminal may be a power or voltage terminal. The signal terminal may be at least partially exposed via a signal terminal opening in the housing when the memory card is accommodated in the slot. The memory card adaptor may also include at least one card-side terminal arranged so as to be capable of contacting at least one of the non-signal terminals.

Abstract: A memory card adaptor is provided herein. The memory card adaptor may include a housing having a slot configured to accommodate a memory card. The memory card may include a signal terminal and non-signal terminals. For example, the signal terminal may be a high-speed and/or data transfer terminal, and the non-signal terminal may be a power or voltage terminal. The signal terminal may be at least partially exposed via a signal terminal opening in the housing when the memory card is accommodated in the slot. The memory card adaptor may also include at least one card-side terminal arranged so as to be capable of contacting at least one of the non-signal terminals.

Abstract: Provided is a complex semiconductor device. The complex semiconductor device includes first memory chips in a first package, second memory chips in a second package configured for mass storage of data, and a controller packaged with either the first package or the second package in a complex package. The controller is connected to the first package via a first internal bus and to the second package via a second internal bus, and the first package, second package and controller are commonly packaged within a single complex package.

Abstract: Provided is a complex semiconductor device. The complex semiconductor device includes first memory chips in a first package, second memory chips in a second package configured for mass storage of data, and a controller packaged with either the first package or the second package in a complex package. The controller is connected to the first package via a first internal bus and to the second package via a second internal bus, and the first package, second package and controller are commonly packaged within a single complex package.

Abstract: A semiconductor package includes: a semiconductor chip having a first surface, and a second surface that is opposite to the first surface and allows a semiconductor device to be formed thereon; bonding pads disposed on the second surface of the semiconductor chip; and a metal ion barrier layer disposed on the first surface of the semiconductor chip, and preventing metal ions from penetrating into the semiconductor chip through the first surface of the semiconductor chip. Accordingly, the semiconductor package can obtain a superior semiconductor device by minimizing moisture absorption and effectively blocking the penetration of metal ions.

Abstract: Integrated circuit memory devices include an array of NAND strings containing a plurality of EEPROM memory cells, sense amplifiers for determining whether the memory cells have been properly erased and programmed during respective erase and program verification modes of operation, an erase voltage adjusting circuit for setting a limit on a range of acceptable erase threshold voltages and a program voltage adjusting circuit for setting a limit on a range of acceptable program threshold voltages. The sense amplifier determines during an erase verification operation whether a memory cell in a NAND string has been erased to have a threshold voltage within a range of acceptable erase threshold voltages. The range of acceptable erase threshold voltages typically has an upper limit less than a predetermined reference potential (e.g., GND). For example, the sense amplifiers can be utilized to determine whether the memory cells in the string have been sufficiently erased so that their erase threshold voltages (EV.sub.

Abstract: A circuit for applying a stress voltage for use in a semiconductor memory device includes a first control circuit for selecting a first block to which a program voltage is applied and then sequentially selecting following blocks; and a second control circuit for selecting a word line to which a stress voltage is to be applied, whereby, in a stress mode for detecting a defective call, the stress voltage is applied to a word line connected to a memory transistor within a first selected memory block and thereafter to word lines in each of the sequentially selected memory blocks.