Patents by Inventor Yong Neo
Yong Neo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7920462Abstract: This disclosure relates to amplitude correction for orthogonal frequency division multiplexing signals received by a communication device. An amplitude attenuation estimation is performed for amplitude correction on received OFDM signals.Type: GrantFiled: October 1, 2007Date of Patent: April 5, 2011Assignee: Infineon Technologies AGInventors: Claus Muschallik, Yun Ye, Jien Mei Loh, Tee Yong Neo
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Publication number: 20090086618Abstract: This disclosure relates to amplitude correction for orthogonal frequency division multiplexing signals received by a communication device. An amplitude attenuation estimation is performed for amplitude correction on received OFDM signals.Type: ApplicationFiled: October 1, 2007Publication date: April 2, 2009Applicant: Infineon Technologies AGInventors: Claus Muschallik, Yun Ye, Jien Mei Loh, Tee Yong Neo
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Publication number: 20070264751Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.Type: ApplicationFiled: July 30, 2007Publication date: November 15, 2007Applicant: MICRON TECHNOLOGY, INC.Inventors: Yong Chia, Suan Boon, Siu Low, Yong Neo, Bok Ser
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Publication number: 20070152327Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.Type: ApplicationFiled: February 28, 2007Publication date: July 5, 2007Applicant: Micron Technology, Inc.Inventors: Yong Chia, Suan Boon, Siu Low, Yong Neo, Bok Ser
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Publication number: 20070145558Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.Type: ApplicationFiled: February 28, 2007Publication date: June 28, 2007Applicant: Micron Technology, Inc.Inventors: Yong Chia, Suan Boon, Siu Low, Yong Neo, Bok Ser
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Publication number: 20070059862Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: ApplicationFiled: November 9, 2006Publication date: March 15, 2007Inventors: Meow Eng, Yong Chia, Yong Neo, Suan Boon, Siu Low, Swee Chua, Shuangwu Huang
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Publication number: 20060001143Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.Type: ApplicationFiled: September 7, 2005Publication date: January 5, 2006Inventors: Suan Boon, Yong Chia, Siu Low, Meow Eng, Swee Chua, Shuang Huang, Yong Neo, Wei Zhou
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Publication number: 20050236709Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: ApplicationFiled: June 30, 2005Publication date: October 27, 2005Inventors: Meow Eng, Yong Chia, Yong Neo, Suan Boon, Siu Low, Swee Chua, Shuangwu Huang
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Publication number: 20050073029Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: November 30, 2004Publication date: April 7, 2005Inventors: Swee Chua, Siu Low, Yong Chia, Meow Eng, Yong Neo, Suan Boon, Shuangwu Huang, Wei Zhou
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Publication number: 20050048695Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.Type: ApplicationFiled: October 12, 2004Publication date: March 3, 2005Applicant: Micron Technology, Inc.Inventors: Yong Chia, Suan Boon, Siu Low, Yong Neo, Bok Ser
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Publication number: 20050006748Abstract: A semiconductor device package is disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: ApplicationFiled: August 4, 2004Publication date: January 13, 2005Inventors: Meow Eng, Yong Chia, Yong Neo, Suan Boon, Siu Low, Swee Chua, Shuangwu Huang