Abstract: A method for exchanging messages is performed by a slave device, and includes: receiving a submission queue (SQ) tail doorbell from a host to learn that X SQ entries need to be processed, wherein “X” doesn't exceed a host SQ entry upper limit; performing multiple read operations according to the SQ tail doorbell to read the X SQ entries from the host, wherein the slave device reads Y SQ entries at most in each read operation, and “Y” is smaller than “X” and doesn't exceed a slave device SQ entry upper limit; preparing P completion queue (CQ) entries; performing multiple write operations to transmit the P CQ entries to the host, wherein the slave device transmits Q CQ entries at most in each write operation, and “Q” is smaller than “P” and doesn't exceed a slave device CQ entry upper limit; and transmitting a CQ tail doorbell to the host.

Abstract: A data encryption and decryption system and a data encryption and decryption method for the same are provided. The system includes a memory controlling circuit and an encryption and decryption circuit. In write operation, the encryption and decryption circuit executes an encryption algorithm on write address to obtain first seed data, executes a first scrambling process on initial write data to generate first scrambled data, and executes a second scrambling process on the first scrambled data according to common seed data, so as to generate encrypted write data. The memory controlling circuit writes the encrypted write data into a memory unit according to the write address.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

Abstract: A method for exchanging messages is performed by a slave device, and includes: receiving a submission queue (SQ) tail doorbell from a host to learn that X SQ entries need to be processed, wherein “X” doesn't exceed a host SQ entry upper limit; performing multiple read operations according to the SQ tail doorbell to read the X SQ entries from the host, wherein the slave device reads Y SQ entries at most in each read operation, and “Y” is smaller than “X” and doesn't exceed a slave device SQ entry upper limit; preparing P completion queue (CQ) entries; performing multiple write operations to transmit the P CQ entries to the host, wherein the slave device transmits Q CQ entries at most in each write operation, and “Q” is smaller than “P” and doesn't exceed a slave device CQ entry upper limit; and transmitting a CQ tail doorbell to the host.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: A power-saving device and method are applicable to a first electronic device having at least one connection interface, and the first electronic device is coupled to a second electronic device via a bus. The power-saving device includes a detection circuit, a power control circuit, and a connection control circuit. The detection circuit is coupled to the connection interface, to detect a load state of the connection interface and generate a detection signal. The power control circuit controls power supplied to the first electronic device via the bus in response to a state of the detection signal. The connection control circuit controls a connection state of the bus according to the detection signal.