Abstract: An antenna and a base station, where the antenna includes: a reflection plate, a radome, a heat sink, a radiating element, and a transceiver. The reflection plate has a first surface and a second surface opposite to each other, the radome is disposed on the first surface of the reflection plate, and the radome and the first surface form an enclosed first accommodating space. The radiating element is disposed in the first accommodating space, so that the first surface of the reflection plate integrates a radome installation function. The heat sink is fastened to the second surface of the reflection plate, and the heat sink and the second surface form an enclosed electromagnetic shielding space. The transceiver is located in the electromagnetic shielding space, so that the second surface of the reflection plate has an electromagnetic shielding function.

Abstract: A power supply processing device includes three electric control valve groups, a positive output terminal and a conversion control switch group. The conversion control switch group includes a selection switch group configured to selectively connect the current valve control components in each electric control valve group to the positive output terminal or the phase output terminal, and a connection switch group configured to connect or disconnect a current path between two electric control valve groups connected one another. In such a way, both AC experiments and DC experiments of high voltage and large capacity may be performed to the connectors without changing experimental site and experimental equipment, thereby effectively reducing the experimental cost.

Abstract: A method for fabricating a semiconductor structure includes when a chip under test releases an ESD current, detecting position information of photons emitted from the chip under test due to releasing of the ESD current; acquiring an image of an ESD path based on the detected position information of the photons; and determining whether the ESD path corresponding to the chip under test is normal based on the image of the ESD path and a layout image of the chip under test.

Abstract: A method for fabricating a semiconductor structure includes when a chip under test releases an ESD current, detecting position information of photons emitted from the chip under test due to releasing of the ESD current; acquiring an image of an ESD path based on the detected position information of the photons; and determining whether the ESD path corresponding to the chip under test is normal based on the image of the ESD path and a layout image of the chip under test.

Abstract: A system and method for facilitating smart power meter monitoring are provided. The system for facilitating smart power meter monitoring includes a standards-based frame detector, a CDR, at least one 8b/10 encoder/decoder and data links to receive input signals and transmit output signals. The system provides for the conversion of incoming SerDes signals, like those that may be transmitted from an optical module, into UART signals that can be communicated to the smart power meter directly through a UART port of the meter. The method includes receiving SerDes signals from an optical module and converting the signals to UART signals. The UART signals are converted to comply with industry standard protocols for communication with the smart power meter. The UART signals are then transmitted to the smart power meter through the meter's UART port.

Abstract: A system and method for facilitating smart power meter monitoring are provided. The system for facilitating smart power meter monitoring includes a standards-based frame detector, a CDR, at least one 8b/10 encoder/decoder and data links to receive input signals and transmit output signals. The system provides for the conversion of incoming SerDes signals, like those that may be transmitted from an optical module, into UART signals that can be communicated to the smart power meter directly through a UART port of the meter. The method includes receiving SerDes signals from an optical module and converting the signals to UART signals. The UART signals are converted to comply with industry standard protocols for communication with the smart power meter. The UART signals are then transmitted to the smart power meter through the meter's UART port.

Abstract: One embodiment of the present invention provides a gallium nitride (GaN)-based semiconductor light-emitting device (LED) which includes an n-type GaN-based semiconductor layer (n-type layer); an active layer; and a p-type GaN-based semiconductor layer (p-type layer). The n-type layer is epitaxially grown by using ammonia gas (NH3) as the nitrogen source prior to growing the active layer and the p-type layer. The flow rate ratio between group V and group III elements is gradually reduced from an initial value to a final value. The GaN-based LED exhibits a reverse breakdown voltage equal to or greater than 60 volts.

Abstract: One embodiment of the present invention provides a gallium nitride (GaN)-based semiconductor light-emitting device (LED) which includes an n-type GaN-based semiconductor layer (n-type layer); an active layer; and a p-type GaN-based semiconductor layer (p-type layer). The n-type layer is epitaxially grown by using ammonia gas (NH3) as the nitrogen source prior to growing the active layer and the p-type layer. The flow rate ratio between group V and group III elements is gradually reduced from an initial value to a final value. The GaN-based LED exhibits a reverse breakdown voltage equal to or greater than 60 volts.

Abstract: A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.

Abstract: A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.