Abstract: A scanning format conversion circuit for performing the mutual conversion between a progressive scanning format and a zig-zag scanning format to read or write N.times.N discrete cosine transform coefficients from or into a memory in a coding process or a decoding process of a video system. The scanning format conversion circuit comprises a pure logic circuit including an up/down counting circuit, a down counting circuit, first to third selection circuits, a comparison circuit, a phase change circuit, and an accumulation circuit. With this construction, the mutual conversion between the progressive scanning format and the zig-zag scanning format is performed on the basis of the rule between the input orders and the actual positions of the discrete cosine transform coefficients. Therefore, the scanning format conversion circuit is capable of simplifying the implementation of ASIC and performing the scanning format conversion operation regardless of a block size.

Abstract: An improved motion vector extractor comprising a first pixel delay element for delaying pixel data of the previous frame by a one pixel interval, a second pixel delay element for delaying the pixel data of the previous frame by a horizontal line interval of a seek block, a third pixel delay element for delaying the pixel data of the previous frame by a seek block horizontal line and one pixel interval, an interpolation circuit for combining the pixel data of the previous frame and the delayed pixel data of the previous frame from the first to third pixel delay elements to produce at least one interpolation pixel data positioned between adjacent ones thereof, a fourth pixel delay element for delaying pixel data of the present frame to produce rectangularly arranged pixel data of the present frame, a plurality of MAD detectors, each of the plurality of MAD detectors subtracting a corresponding one of the interpolation pixel data from the interpolation circuit from a corresponding one of the rectangularly arrang