Patents by Inventor Yong-Seok Ahn
Yong-Seok Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11594538Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.Type: GrantFiled: September 8, 2021Date of Patent: February 28, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Ho Lee, Eun A Kim, Ki Seok Lee, Jay-Bok Choi, Keun Nam Kim, Yong Seok Ahn, Jin-Hwan Chun, Sang Yeon Han, Sung Hee Han, Seung Uk Han, Yoo Sang Hwang
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Patent number: 11393825Abstract: A semiconductor device includes a substrate having a cell region, a boundary region, a peripheral region sequentially arranged in a first direction, an active pattern extending in the cell region in a second direction forming a first acute angle with respect to the first direction, and a boundary pattern in the cell region and directly adjacent to the boundary region. The boundary pattern includes a first side surface extending in the second direction and a first boundary surface extending in a third direction, which is perpendicular to the first direction, from the first side surface, and the first boundary surface defines a boundary between the cell region and the boundary region.Type: GrantFiled: May 29, 2020Date of Patent: July 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jay-Bok Choi, Su Ji Ahn, Yong Seok Ahn, Seung Hyung Lee
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Publication number: 20210408004Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.Type: ApplicationFiled: September 8, 2021Publication date: December 30, 2021Inventors: Sang Ho LEE, Eun A KIM, Ki Seok LEE, Jay-Bok CHOI, Keun Nam KIM, Yong Seok AHN, Jin-Hwan CHUN, Sang Yeon HAN, Sung Hee HAN, Seung Uk HAN, Yoo Sang HWANG
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Patent number: 11121134Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.Type: GrantFiled: April 28, 2020Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Ho Lee, Eun A Kim, Ki Seok Lee, Jay-Bok Choi, Keun Nam Kim, Yong Seok Ahn, Jin-Hwan Chun, Sang Yeon Han, Sung Hee Han, Seung Uk Han, Yoo Sang Hwang
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Publication number: 20210118886Abstract: A semiconductor device includes a substrate having a cell region, a boundary region, a peripheral region sequentially arranged in a first direction, an active pattern extending in the cell region in a second direction forming a first acute angle with respect to the first direction, and a boundary pattern in the cell region and directly adjacent to the boundary region. The boundary pattern includes a first side surface extending in the second direction and a first boundary surface extending in a third direction, which is perpendicular to the first direction, from the first side surface, and the first boundary surface defines a boundary between the cell region and the boundary region.Type: ApplicationFiled: May 29, 2020Publication date: April 22, 2021Inventors: Jay-Bok CHOI, Su Ji AHN, Yong Seok AHN, Seung Hyung LEE
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Publication number: 20210098460Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.Type: ApplicationFiled: April 28, 2020Publication date: April 1, 2021Inventors: Sang Ho LEE, Eun A KIM, Ki Seok LEE, Jay-Bok CHOI, Keun Nam KIM, Yong Seok AHN, Jin-Hwan CHUN, Sang Yeon HAN, Sung Hee HAN, Seung Uk HAN, Yoo Sang HWANG
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Patent number: 7329918Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.Type: GrantFiled: May 22, 2006Date of Patent: February 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Cho, Tae-Young Chung, Yong-Seok Ahn
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Publication number: 20060211192Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.Type: ApplicationFiled: May 22, 2006Publication date: September 21, 2006Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Hyun Cho, Tae-Young Chung, Yong-Seok Ahn
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Patent number: 7074667Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.Type: GrantFiled: May 11, 2004Date of Patent: July 11, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Cho, Tae-Young Chung, Yong-Seok Ahn
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Publication number: 20040229428Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.Type: ApplicationFiled: May 11, 2004Publication date: November 18, 2004Inventors: Chang-Hyun Cho, Tae-Young Chung, Yong-Seok Ahn