Patents by Inventor Yong-Seok Chung

Yong-Seok Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10163976
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Seok Suh, Jae-Chul Shim, Kil-Ho Lee, Yong-Seok Chung, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 10103323
    Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: October 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Seok Chung, Yoonjong Song, Yongkyu Lee, Gwanhyeob Koh
  • Patent number: 9928892
    Abstract: A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: March 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-young Seo, Yong-seok Chung, Gwan-hyeob Koh, Yong-kyu Lee
  • Publication number: 20180012933
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 11, 2018
    Inventors: Ki-Seok SUH, Jae-Chul SHIM, Kil-Ho LEE, Yong-Seok CHUNG, Gwan-Hyeob KOH, Yoon-Jong SONG
  • Publication number: 20180013060
    Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.
    Type: Application
    Filed: September 14, 2017
    Publication date: January 11, 2018
    Inventors: Yong-Seok CHUNG, YOONJONG SONG, YONGKYU LEE, GWANHYEOB KOH
  • Patent number: 9853087
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: December 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Seok Suh, Jae-Chul Shim, Kil-Ho Lee, Yong-Seok Chung, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 9793472
    Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Seok Chung, Yoonjong Song, Yongkyu Lee, Gwanhyeob Koh
  • Publication number: 20170069684
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Application
    Filed: May 17, 2016
    Publication date: March 9, 2017
    Inventors: Ki-Seok SUH, Jae-Chul SHIM, Kil-Ho LEE, Yong-Seok CHUNG, Gwan-Hyeob KOH, Yoon-Jong SONG
  • Publication number: 20170053688
    Abstract: A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.
    Type: Application
    Filed: May 13, 2016
    Publication date: February 23, 2017
    Inventors: Bo-young SEO, Yong-seok CHUNG, Gwan-hyeob KOH, Yong-kyu LEE
  • Publication number: 20170040531
    Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.
    Type: Application
    Filed: June 10, 2016
    Publication date: February 9, 2017
    Inventors: Yong-Seok CHUNG, YOONJONG SONG, YONGKYU LEE, GWANHYEOB KOH
  • Patent number: 7932149
    Abstract: In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jeong-Uk Han, Jae-Min Yu, Young-Cheon Jeong, Sang-Hoon Park, Kwan-Jong Roh, Byeong-Cheol Lim, Yong-Seok Chung
  • Publication number: 20090286369
    Abstract: In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
    Type: Application
    Filed: May 19, 2009
    Publication date: November 19, 2009
    Inventors: Jee-Hyun Park, Jeong-Uk Han, Jae-Min Yu, Young-Cheon Jeong, Sang-Hoon Park, Kwan-Jong Roh, Byeong-Cheol Lim, Yong-Seok Chung
  • Patent number: 6094317
    Abstract: A method for controlling a data read/write operation of a disk drive recording device provided with re-allocated reserve sectors as a substitute for defective sectors, includes the steps of: reading data written on the reserve sectors when turning the power on and further storing the data, and disposing the data stored after being retrieved from the re-allocated reserve sectors as a substitute for defective sectors to the rear of data retrieved from a sector preceding the defective sector when accessing a random data section containing the defective sector, and further transferring the resulting data.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: July 25, 2000
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Yong-Seok Chung
  • Patent number: D578909
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: October 21, 2008
    Assignee: Planet 82 Inc.
    Inventors: Yong-Seok Chung, Young-Seok Bae, Young-Bin Kim, Jin-Seok Kim