Abstract: Provided is a cosmetic composition for blocking infrared rays and ultraviolet rays at the same time, the cosmetic composition including an inorganic material which blocks ultraviolet rays, an inorganic material which blocks infrared rays, and a dispersing agent.

Abstract: The present invention relates to a cosmetic comprising polyurethane foam in which a liquid cosmetic substance is impregnated. The present invention provides a cosmetic comprising polyurethane foam in which a cosmetic composition is impregnated, wherein the polyurethane of the polyurethane foam comprises an ether group and an ester group in a molar ratio of 4:6 to 6:4, the ?<cosmetic composition has a water content of 35 wt % or less, and the threshold shear stress at which storage modulus (G?)=loss modulus (G?) is 100 Pa or less. According to the present invention, provided is a cosmetic comprising a composite polyurethane foam, wherein a cosmetic composition is stably present in a supported state and can be uniformly rearranged inside the foam during pressurization.

Abstract: As an ejector of the present disclosure and a cooling apparatus having the same include a suction guide unit at least partially having a curved surface so that the ejector guides a flow of a refrigerant, a structure is improved and thus a flow loss can be reduced. Also, through the improved structure, a mixture rate between a refrigerant passing through a nozzle unit and a refrigerant passing through a suction unit is improved, so that pressure rising efficiency can be increased to reduce a compressor load, and thus energy efficiency can be increased due to an increase in efficiency of the ejector.

Abstract: Disclosed herein is a refrigeration cycle includes a first refrigerant circuit configured to cause a refrigerant ejected from a compressor to flow through a condenser, an ejector, a first evaporator, and a second evaporator and flow back to the compressor; a second refrigerant circuit configured to cause the refrigerant to bypass the first evaporator in the first refrigerant circuit; and a third refrigerant circuit branching at a junction provided at a downstream end of the condenser from at least one of the first refrigerant circuit and the second refrigerant circuit, and configured to cause the refrigerant to flow through an expansion device and a third evaporator and flow to the ejector. By such configuration, a coefficient of performance (COP) of a refrigeration cycle may be improved and an ejector may be used to improve energy efficiency.

Abstract: Disclosed herein is a refrigeration cycle includes a first refrigerant circuit configured to cause a refrigerant ejected from a compressor to flow through a condenser, an ejector, a first evaporator, and a second evaporator and flow back to the compressor; a second refrigerant circuit configured to cause the refrigerant to bypass the first evaporator in the first refrigerant circuit; and a third refrigerant circuit branching at a junction provided at a downstream end of the condenser from at least one of the first refrigerant circuit and the second refrigerant circuit, and configured to cause the refrigerant to flow through an expansion device and a third evaporator and flow to the ejector. By such configuration, a coefficient of performance (COP) of a refrigeration cycle may be improved and an ejector may be used to improve energy efficiency.

Abstract: As an ejector of the present disclosure and a cooling apparatus having the same include a suction guide unit at least partially having a curved surface so that the ejector guides a flow of a refrigerant, a structure is improved and thus a flow loss can be reduced. Also, through the improved structure, a mixture rate between a refrigerant passing through a nozzle unit and a refrigerant passing through a suction unit is improved, so that pressure rising efficiency can be increased to reduce a compressor load, and thus energy efficiency can be increased due to an increase in efficiency of the ejector.

Abstract: A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines.

Abstract: A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines.