Abstract: An apparatus for locking a portable computer includes an apparatus body, a first clamping member rotatably coupled to the apparatus body, configured to support a first side of a computer body of the portable computer, and configured to be fitted over a first edge of a display of the portable computer, a slider coupled to the apparatus body to be reciprocally movable, a second clamping member rotatably coupled to the slider while being spaced apart from the first clamping member, configured to support a second side of the computer body of the portable computer, and configured to be fitted over a second edge of the display of the portable computer, and a locking and unlocking unit installed on the apparatus body and configured to selectively restrict or allow movement of the slider.

Abstract: A buffer unit for temporarily storing a substrate includes a housing having a space for storing a substrate therein, one or more slots disposed within the housing for placing a substrate thereon, and a holding unit disposed at a bottom portion of the housing, having a flat and non-inclined top surface, and comprising a built-in wireless charging module. A substrate type sensor is stored at the holding unit.

Abstract: An apparatus for locking a portable computer includes an apparatus body, a first clamping member rotatably coupled to the apparatus body, configured to support a first side of a computer body of the portable computer, and configured to be fitted over a first edge of a display of the portable computer, a slider coupled to the apparatus body to be reciprocally movable, a second clamping member rotatably coupled to the slider while being spaced apart from the first clamping member, configured to support a second side of the computer body of the portable computer, and configured to be fitted over a second edge of the display of the portable computer, and a locking and unlocking unit installed on the apparatus body and configured to selectively restrict or allow movement of the slider.

Abstract: A level shifter includes an input control unit suitable for outputting an output control signal according to a pulse width of a data signal and a pulse width of an input control signal; and an output control unit suitable for controlling an output driving signal according to the output control signal.

Abstract: A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being parallel with the rows and including a couple of first selection lines connected to each of the local blocks, second selection lines disposed in parallel with the columns, and local block selectors disposed between the plurality of local blocks. Each of the local block selectors is disposed between a Qth wherein, “Q” is an odd number local block and a (Q+1)th local block among the local blocks to electrically connect unit cells disposed in any one of the Qth local block and the (Q+1)th local block to the second selection lines. The unit cells in the local blocks are disposed at cross points of the first selection lines and the second selection lines, respectively. Each of the unit cells includes a P-channel MOSFET.

Abstract: A level shifter includes an input control unit suitable for outputting an output control signal according to a pulse width of a data signal and a pulse width of an input control signal; and an output control unit suitable for controlling an output driving signal according to the output control signal.

Abstract: An EPROM cell array includes a cell array including multiple unit cells, each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns; multiple first selection lines each coupled with drains of unit cells, which are disposed on the same row among the multiple unit cells; and multiple second selection lines each coupled with sources of unit cells, which are disposed on the same column among the unit cells, wherein a selected unit cell to be programmed or read is selected by one of the multiple first selection lines, and one of the multiple second selection lines.

Abstract: A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being parallel with the rows and including a couple of first selection lines connected to each of the local blocks, second selection lines disposed in parallel with the columns, and local block selectors disposed between the plurality of local blocks. Each of the local block selectors is disposed between a Qth wherein, “Q” is an odd number local block and a (Q+1)th local block among the local blocks to electrically connect unit cells disposed in any one of the Qt local block and the (Q+1)th local block to the second selection lines. The unit cells in the local blocks are disposed at cross points of the first selection lines and the second selection lines, respectively. Each of the unit cells includes a P-channel MOSFET.

Abstract: An EPROM cell array includes a cell array including multiple unit cells, each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns; multiple first selection lines each coupled with drains of unit cells, which are disposed on the same row among the multiple unit cells; and multiple second selection lines each coupled with sources of unit cells, which are disposed on the same column among the unit cells, wherein a selected unit cell to be programmed or read is selected by one of the multiple first selection lines, and one of the multiple second selection lines

Abstract: A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal.

Abstract: An apparatus selectively outputs one negative voltage from among a plurality of negative voltages. The apparatus includes a first switching unit configured to perform a switching operation and output a first voltage-on signal and a first voltage-off signal according to a selection signal and a first negative voltage signal, and a second switching unit configured to perform a switching operation and to output a second voltage-on signal and a second voltage-off signal according to the selection signal and a second negative voltage signal. The apparatus also includes a driving unit to select and output one negative voltage signal from among the first and second negative voltage signals according to the first negative voltage signal, the second negative voltage signal, the first voltage-on signal, the first voltage-off signal, the second voltage-on signal, and the second voltage-off signal.

Abstract: An apparatus selectively outputs one negative voltage from among a plurality of negative voltages. The apparatus includes a first switching unit configured to perform a switching operation and output a first voltage-on signal and a first voltage-off signal according to a selection signal and a first negative voltage signal, and a second switching unit configured to perform a switching operation and to output a second voltage-on signal and a second voltage-off signal according to the selection signal and a second negative voltage signal. The apparatus also includes a driving unit to select and output one negative voltage signal from among the first and second negative voltage signals according to the first negative voltage signal, the second negative voltage signal, the first voltage-on signal, the first voltage-off signal, the second voltage-on signal, and the second voltage-off signal.

Abstract: A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal.

Abstract: A stable and reliable EEPROM device includes an EEPROM cell having first, second and third control voltage terminals for performing operations for programming, reading and erasing data, respectively, a first transistor configured to supply a programming operation voltage to the first control voltage terminal during the programming operation, a second transistor configured to supply a ground voltage to the first control voltage terminal, the data of which will not be programmed during the programming operation, and a third transistor connected to the second control voltage terminal and turned on by an address selected for reading the data of the EEPROM cell during the reading operation.

Abstract: A stable and reliable EEPROM device includes an EEPROM cell having first, second and third control voltage terminals for performing operations for programming, reading and erasing data, respectively, a first transistor configured to supply a programming operation voltage to the first control voltage terminal during the programming operation, a second transistor configured to supply a ground voltage to the first control voltage terminal, the data of which will not be programmed during the programming operation, and a third transistor connected to the second control voltage terminal and turned on by an address selected for reading the data of the EEPROM cell during the reading operation.

Abstract: A miniaturized system on a chip that incorporates a positive high voltage charge pump and a negative high voltage charge pump into one pump circuit and shares components. A voltage control apparatus in a semiconductor device may include at least one of the following: First and second input/output units capable of inputting or outputting voltage. A voltage booster that receives and boosts a voltage from one of the first and second input/output unit and outputs the boosted voltage from the other input/output unit. An output selector that receives the boosted voltage from the voltage booster and selects one of the positive or the negative voltage to output. An output controller that receives the boosted voltage from the voltage booster and controls and/or regulates the output voltage. An output unit that outputs the generated output voltage.

Abstract: The present invention relates to a method and apparatus for trimming a reference voltage. The method may include at least one steep of performing an erase operation of a flash memory resistor; performing a program operation of the flash memory resistor; performing a current read operation of the flash memory resistor; confirming the threshold voltage of the flash memory resistor by measuring the current flowing into a drain of the flash memory resistor; determining whether the threshold voltage of the flash memory resistor satisfies a reference voltage; and then completing the trimming operation if the threshold voltage of the flash memory resistor satisfies the reference voltage.

Abstract: Disclosed is a voltage switch circuit of a semiconductor device. The subject voltage switch circuit can be used to apply voltage to a semiconductor memory device control circuit. The voltage switch circuit according to an embodiment includes five transistors and a capacitor. An output terminal of the subject circuit outputs VSS when VDD is applied to an input terminal, and outputs a boosted operating voltage when VSS is applied to the input terminal.

Abstract: Disclosed is a voltage switch circuit of a semiconductor device. The subject voltage switch circuit can be used to apply voltage to a semiconductor memory device control circuit. The voltage switch circuit according to an embodiment includes five transistors and a capacitor. An output terminal of the subject circuit outputs VSS when VDD is applied to an input terminal, and outputs a boosted operating voltage when VSS is applied to the input terminal.

Abstract: A miniaturized system on a chip that incorporates a positive high voltage charge pump and a negative high voltage charge pump into one pump circuit and shares components. A voltage control apparatus in a semiconductor device may include at least one of the following: First and second input/output units capable of inputting or outputting voltage. A voltage booster that receives and boosts a voltage from one of the first and second input/output unit and outputs the boosted voltage from the other input/output unit. An output selector that receives the boosted voltage from the voltage booster and selects one of the positive or the negative voltage to output. An output controller that receives the boosted voltage from the voltage booster and controls and/or regulates the output voltage. An output unit that outputs the generated output voltage.