Abstract: Disclosed are a wire rod and a component, for cold forging, each having excellent delayed fracture resistance characteristics and applicable to high-strength bolts and the like and a manufacturing method therefor. According to an embodiment, a heat-treated component having excellent delayed fracture resistance characteristics includes, in percent by weight (wt %), 0.3 to 0.5% of C, 0.01 to 0.3% of Si, 0.3 to 1.0% of Mn, at least two types selected from the group consisting of 0.3 to 1.5% of Cr, 0.3 to 1.5% of Mo, and 0.01 to 0.4% of V, and the balance being Fe and other impurities, includes, as a microstructure, a tempered martensite phase in an area fraction of 95% or more, and includes V-based carbides having a diameter of 300 nm or less at 10/100 ?m2 or more.

Abstract: A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters and perform a test on at least one memory core. The method includes setting a sweep range including a sweep start point of a first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: There is provided a rolled steel with excellent toughness, a drawn wire rod prepared by drawing the rolled steel, and a method for manufacturing the same, in which even if a heating step is omitted, the toughness of the steel can be improved by securing a degenerated pearlite structure in an internal structure of the rolled steel by controlling a content of Mn among components and cooling conditions, and then preventing C diffusion. The rolled steel according to the present invention includes C: 0.15˜0.30%, Si: 0.1˜0.2%, Mn: 1.8˜3.0%, P: 0.035% or less, S: 0.040% or less, the remainder Fe, and other inevitable impurites, as a percentage of weight, in which the microstucture of the rolled steel is composed of ferrite and pearlite including cementite with 150 nm or less of thickness.

Abstract: There is provided a rolled steel with excellent toughness, a drawn wire rod prepared by drawing the rolled steel, and a method for manufacturing the same, in which even if a heating step is omitted, the toughness of the steel can be improved by securing a degenerated pearlite structure in an internal structure of the rolled steel by controlling a content of Mn among components and cooling conditions, and then preventing C diffusion. The rolled steel according to the present invention includes C: 0.15˜0.30%, Si: 0.1˜0.2%, Mn: 1.8˜3.0%, P: 0.035% or less, S: 0.040% or less, the remainder Fe, and other inevitable impurites, as a percentage of weight, in which the microstucture of the rolled steel is composed of ferrite and pearlite including cementite with 150 nm or less of thickness.

Abstract: An approach is disclosed for providing a humanoid joint for a robotic system. A joint apparatus includes a supporting part, a rotating part and a pair of joint part, wherein the supporting part and the rotating part are coupled in which the joint part is disposed, wherein a rotational force is initially driven by a joint part and the rotational force is transmitted to the other joint part using a sliding motion generated at an abutted surface of each joint part, wherein the surface is formed at the end of the joint part, wherein the transmitted rotational forces can be converted into a motion by the restriction of movement of joint part occurred within the limited space formed by the coupling of rotational part and supporting part.

Abstract: A computer system provided with a cable manager capable of connecting or disconnecting a variety of peripheral devices to or from a computer of the computer system by a single operation thereof, includes: a single integrated connector connected to a computer of the computer system, a plurality of peripheral device ports connected to respective ports of the peripheral devices, the peripheral device ports having a variety of shapes, a LAN modular connector for connecting the computer to a LAN server, and a LAN client card connected to the LAN modular connector.

Abstract: An optical disk is provided including a read only memory region formed on one surface of the optical disk and recorded with information, a non-volatile memory formed on the other surface of the optical disk opposite to the surface formed with the read only memory region, a mark formed on the surface of the optical disk where the non-volatile memory is formed, and one or more dummy memories arranged on the optical disk in such a manner that the center of weight of the optical disk is positioned at the center of the optical disk. Also, provided is an optical disk unit adapted to use the optical disk, which includes a non-volatile memory pickup unit for reading data recorded on the non-volatile memory of the optical disk and writing data onto the non-volatile memory.

Abstract: An apparatus and a method for monitoring the state of a battery are disclosed in which a micro-processor is used to accurately measure the current state of a battery used for supplying electric power in electric automobiles and the like. The present invention includes: a plurality of passive modules with a micro-processor installed thereon for measuring the charge state of respective batteries; an active module for measuring the overall state of the batteries and for supervising the respective passive modules; and serial lines for connecting the passive modules and the active module. The passive modules compute the charge/discharge states of the respective batteries within certain time intervals to record the data into an internal RAM. The active module measures the overall charge/discharge state of the total batteries within certain time intervals, and receives the data on the charge/discharge states of the individual batteries through the serial communications.