Patents by Inventor Yong-Sik Yim
Yong-Sik Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8485081Abstract: Synthetic fiber rope for a crane, include a central strand having an inner core made of a synthetic resin and an inner cover made of synthetic fibers and connected to the inner core via braiding, a plurality of outer strands each of which includes an outer core made of a synthetic resin and an outer cover made of synthetic fibers and connected to the outer core via twisting and which are connected to the outer surface of the central strand via braiding, and a jacket made of synthetic fibers and braided to cover the surface of the plurality of outer strands. Method of manufacturing a synthetic fiber rope is also disclosed.Type: GrantFiled: April 12, 2012Date of Patent: July 16, 2013Assignee: DSR Corp.Inventors: Do-kyoun Kim, Yong-sik Yim
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Publication number: 20120260620Abstract: Synthetic fiber rope for a crane, include a central strand having an inner core made of a synthetic resin and an inner cover made of synthetic fibers and connected to the inner core via braiding, a plurality of outer strands each of which includes an outer core made of a synthetic resin and an outer cover made of synthetic fibers and connected to the outer core via twisting and which are connected to the outer surface of the central strand via braiding, and a jacket made of synthetic fibers and braided to cover the surface of the plurality of outer strands. Method of manufacturing a synthetic fiber rope is also disclosed.Type: ApplicationFiled: April 12, 2012Publication date: October 18, 2012Applicant: DSR CORP.Inventors: Do-kyoun KIM, Yong-sik Yim
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Patent number: 8114778Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.Type: GrantFiled: October 15, 2010Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-yong Park, Jae-kwan Park, Yong-sik Yim, Jae-hwang Sim
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Publication number: 20110034030Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.Type: ApplicationFiled: October 15, 2010Publication date: February 10, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-yong Park, Jae-kwan Park, Yong-sik Yim, Jaw-hwang Sim
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Patent number: 7816270Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.Type: GrantFiled: May 6, 2009Date of Patent: October 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-yong Park, Jae-kwan Park, Yong-sik Yim, Jae-hwang Sim
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Publication number: 20090286404Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.Type: ApplicationFiled: May 6, 2009Publication date: November 19, 2009Inventors: Sang-yong Park, Jae-kwan Park, Yong-sik Yim, Jae-Hwang Sim
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Patent number: 7611948Abstract: A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.Type: GrantFiled: November 27, 2007Date of Patent: November 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Sim, Yong-Sik Yim, Ki-Nam Kim, Jae-Kwan Park
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Publication number: 20090236651Abstract: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.Type: ApplicationFiled: May 11, 2009Publication date: September 24, 2009Inventors: Dong Hwa Kwak, Jae-Kwan Park, Yong-Sik Yim, Won-Cheol Jeong, Jae-Hwang Sim
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Patent number: 7544565Abstract: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.Type: GrantFiled: December 20, 2006Date of Patent: June 9, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hwa Kwak, Jae-Kwan Park, Yong-Sik Yim, Won-Cheol Jeong, Jae-Hwang Sim
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Patent number: 7508048Abstract: Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region.Type: GrantFiled: January 15, 2004Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Woong Kang, Hong-Soo Kim, Jung-Dal Choi, Kyu-Charn Park, Seong-Soon Cho, Yong-Sik Yim, Sung-Nam Chang
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Publication number: 20080160693Abstract: A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.Type: ApplicationFiled: November 27, 2007Publication date: July 3, 2008Inventors: Jae-Hwang Sim, Yong-Sik Yim, Ki-Nam Kim, Jae-Kwan Park
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Publication number: 20080057644Abstract: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.Type: ApplicationFiled: December 20, 2006Publication date: March 6, 2008Inventors: Dong-Hwa Kwak, Jae-Kwan Park, Yong-Sik Yim, Won-Cheol Jeong, Jae-Hwang Sim
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Publication number: 20040145020Abstract: Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region.Type: ApplicationFiled: January 15, 2004Publication date: July 29, 2004Inventors: Dae-Woong Kang, Hong-Soo Kim, Jung-Dal Choi, Kyu-Charn Park, Seong-Soon Cho, Yong-Sik Yim, Sung-Nam Chang
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Patent number: 6753572Abstract: A floating trap type non-volatile memory device and fabrication method thereof are provided. The floating trap type device comprises a substrate, a gate electrode formed on the substrate. A charge storage layer is interposed between the substrate and the gate electrode. A tunneling layer is interposed between the substrate and charge storage layer. The charge storage layer comprises a material having a narrower band gap than silicon nitride. The charge storage layer preferably formed of tetrahedral amorphous carbon. The potential barrier between the charge storage layer and the tunneling layer is increased by using the tetrahedral amorphous carbon as the charge storage layer. Therefore, the charge retention characteristic of the floating trap type device is improved.Type: GrantFiled: July 2, 2002Date of Patent: June 22, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-Dal Choi, Yong-Sik Yim
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Patent number: 6750525Abstract: A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure is provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can also be thinner than the equivalent thickness of the cell gate insulation layer.Type: GrantFiled: March 15, 2002Date of Patent: June 15, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi, Hong-Suk Kwack, You-Cheol Shin
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Patent number: 6734065Abstract: Embodiments of the invention provide a method that includes forming a selection transistor and a cell transistor that includes a cell gate insulation layer in a cell array area. The method also includes forming a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer in a peripheral circuit area. The low-voltage gate insulation layer is formed thinner than the high-voltage gate insulation layer. The low voltage gate insulation layer may also be formed thinner than the equivalent thickness of the cell gate insulation layer.Type: GrantFiled: April 18, 2003Date of Patent: May 11, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi, Hong-Suk Kwack, You-Cheol Shin
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Publication number: 20030205728Abstract: A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure and a fabrication method thereof are provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can be also thinner than the equivalent thickness of the cell gate insulation layer.Type: ApplicationFiled: April 18, 2003Publication date: November 6, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi, Hong-Suk Kwack, You-Cheol Shin
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Patent number: 6576513Abstract: A NAND-type flash memory device for preventing punchthrough and a method for forming the same are provided. The NAND-type flash memory device includes a string selection transistor, a plurality of cell memory transistors, and a ground selection transistor being sequentially connected in series. The device further includes a bitline contact connected to a drain region of the string selection transistor, and a common source line connected to a source region of the ground selection transistor. Impurities are heavily doped to a drain-to-channel interface in the string selection transistor and a channel-to-source interface in the ground selection transistor, forming pockets for preventing punchthrough. The pockets are preferably formed using a tilted ion implantation using the vertical gate structures as masks.Type: GrantFiled: October 16, 2002Date of Patent: June 10, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi
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Patent number: 6567308Abstract: A NAND-type flash memory device for preventing punchthrough and a method for forming the same are provided. The NAND-type flash memory device includes a string selection transistor, a plurality of cell memory transistors, and a ground selection transistor being sequentially connected in series. The device further includes a bitline contact connected to a drain region of the string selection transistor, and a common source line connected to a source region of the ground selection transistor. Impurities are heavily doped to a drain-to-channel interface in the string selection transistor and a channel-to-source interface in the ground selection transistor, forming pockets for preventing punchthrough. The pockets are preferably formed using a tilted ion implantation using the vertical gate structures as masks.Type: GrantFiled: September 26, 2001Date of Patent: May 20, 2003Assignee: Samsung Electronic Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi
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Patent number: 6521941Abstract: A non-volatile memory device and fabrication methods thereof are provided. A first inter-gate insulating layer is formed to intervene between control gate electrodes and floating gate electrodes in a cell array area. A second inter-gate insulating layer is formed to intervene between a gate electrode and a dummy gate electrode in a peripheral circuit area. The second inter-gate insulating layer has a thickness greater than a thickness of the first inter-gate insulating layer on a top surface of the floating gate electrodes. By reducing the difference between the thickness of the first inter-gate insulating layer on sidewalls of floating gate patterns and the thickness of the second inter-gate insulating layer on a gate electrode pattern, in accordance with the invention, any etching damage to the substrate in the peripheral circuit area can be considerably reduced or prevented during the fabrication process.Type: GrantFiled: May 17, 2001Date of Patent: February 18, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Charn Park, Jung-Dal Choi, Yong-Sik Yim