Patents by Inventor Yong Soo Joung
Yong Soo Joung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11462545Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.Type: GrantFiled: January 21, 2020Date of Patent: October 4, 2022Assignee: SK hynix Inc.Inventors: Il-Sik Jang, Ji-Hwan Park, Mi-Ri Lee, Bong-Seok Jeon, Yong-Soo Joung, Sun-Hwan Hwang
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Publication number: 20200161307Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.Type: ApplicationFiled: January 21, 2020Publication date: May 21, 2020Inventors: Il-Sik JANG, Ji-Hwan PARK, Mi-Ri LEE, Bong-Seok JEON, Yong-Soo JOUNG, Sun-Hwan HWANG
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Patent number: 10559569Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.Type: GrantFiled: September 11, 2017Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventors: Il-Sik Jang, Ji-Hwan Park, Mi-Ri Lee, Bong-Seok Jeon, Yong-Soo Joung, Sun-Hwan Hwang
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Publication number: 20180175042Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.Type: ApplicationFiled: September 11, 2017Publication date: June 21, 2018Inventors: Il-Sik JANG, Ji-Hwan PARK, Mi-Ri LEE, Bong-Seok JEON, Yong-Soo JOUNG, Sun-Hwan HWANG
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Patent number: 8999797Abstract: A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers on sidewalls of the contact holes, forming first plugs recessed inside the contact holes, forming air gaps by removing the sacrificial spacers, forming conductive capping layers capping the first plugs and the air gaps, and forming second plugs over the conductive capping layers.Type: GrantFiled: August 7, 2014Date of Patent: April 7, 2015Assignee: SK Hynix Inc.Inventors: Yong-Soo Joung, Hyung-Kyun Kim, Jae-Soo Kim, Dong-Gun Hwang, Kyoung Yoo
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Publication number: 20140357076Abstract: A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers on sidewalls of the contact holes, forming first plugs recessed inside the contact holes, forming air gaps by removing the sacrificial spacers, forming conductive capping layers capping the first plugs and the air gaps, and forming second plugs over the conductive capping layers.Type: ApplicationFiled: August 7, 2014Publication date: December 4, 2014Inventors: Yong-Soo JOUNG, Hyung-Kyun KIM, Jae-Soo KIM, Dong-Gun HWANG, Kyoung YOO
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Patent number: 8828829Abstract: A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers on sidewalls of the contact holes, forming first plugs recessed inside the contact holes, forming air gaps by removing the sacrificial spacers, forming conductive capping layers capping the first plugs and the air gaps, and forming second plugs over the conductive capping layers.Type: GrantFiled: March 16, 2013Date of Patent: September 9, 2014Assignee: SK Hynix Inc.Inventors: Yong-Soo Joung, Hyung-Kyun Kim, Jae-Soo Kim, Dong-Gun Hwang, Kyoung Yoo
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Publication number: 20140179102Abstract: A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers on sidewalls of the contact holes, forming first plugs recessed inside the contact holes, forming air gaps by removing the sacrificial spacers, forming conductive capping layers capping the first plugs and the air gaps, and forming second plugs over the conductive capping layers.Type: ApplicationFiled: March 16, 2013Publication date: June 26, 2014Applicant: SK hynix Inc.Inventors: Yong-Soo JOUNG, Hyung-Kyun KIM, Jae-Soo KIM, Dong-Gun HWANG, Kyoung YOO
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Publication number: 20120208335Abstract: Methods of fabricating a semiconductor device are provided. The method includes forming a first gate stack and a second gate stack on a first region and a second region of a substrate, respectively. The method may further comprise forming first impurity regions self-aligned with the first gate stack and second impurity regions self-aligned with the second gate stack in the substrate of the first region and in the substrate of the second region, respectively. First impurity ions may be injected into the first and second impurity regions, forming a mask pattern covering the first region and exposing the second region on the substrate where the first impurity ions are injected and second impurity ions having an opposite conductivity type to the first impurity ions may be injected into the second impurity regions exposed by the mask pattern using a plasma doping process. The mask pattern may then be removed.Type: ApplicationFiled: February 14, 2012Publication date: August 16, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyong Bong ROUH, Ho Jin CHO, Yong Soo JOUNG
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Patent number: 7855113Abstract: A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug.Type: GrantFiled: June 22, 2009Date of Patent: December 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yong Soo Joung, Seung Woo Jin, An Bae Lee, Young Hwan Joo
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Patent number: 7824975Abstract: A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer.Type: GrantFiled: June 30, 2008Date of Patent: November 2, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yong Soo Joung, Kyoung Bong Rouh, Hye Jin Seo
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Patent number: 7807513Abstract: Methods for manufacturing a semiconductor device are provided that reduces the thickness of an oxide layer formed on a polysilicon layer for bit line contacts. A reduced thickness oxide layer can prevent short circuits between adjoining bit lines. A reduced thickness oxide layer can also eliminate the need for overetching in a subsequent etching process, thereby preventing loss of an isolation layer in a peripheral region.Type: GrantFiled: December 28, 2009Date of Patent: October 5, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyung Kyun Kim, Yong Soo Joung
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Publication number: 20100190326Abstract: A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug.Type: ApplicationFiled: June 22, 2009Publication date: July 29, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yong Soo Joung, Seung Woo Jin, An Bae Lee, Young Hwan Joo
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Publication number: 20090170297Abstract: A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer.Type: ApplicationFiled: June 30, 2008Publication date: July 2, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yong Soo Joung, Kyoung Bong Rouh, Hye Jin Seo
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Patent number: 7538003Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a semiconductor substrate, forming a gate stack on the channel region, and feeding hydrogen into junctions of the source and drain regions to neutralize dopants of the first conductivity type present within particular portions of the junctions.Type: GrantFiled: December 28, 2006Date of Patent: May 26, 2009Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Min Yong Lee, Yong Soo Joung
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Publication number: 20080003756Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a semiconductor substrate, forming a gate stack on the channel region, and feeding hydrogen into junctions of the source and drain regions to neutralize dopants of the first conductivity type present within particular portions of the junctions.Type: ApplicationFiled: December 28, 2006Publication date: January 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Min Yong Lee, Yong Soo Joung