Abstract: In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Abstract: A display device includes a display panel, a data driving part and a gate driving part. The display panel includes a first pixel row. The first pixel row includes a first pixel connected to an (n+1)-th gate line and an (m+1)-th data line (where ‘n’ and ‘m’ are natural numbers), and a second pixel connected to an n-th gate line and an (m+2)-th data line. The data driving part applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line, and applies a data voltage having a second polarity with respect to the reference voltage to the (m+2)-th data line. The gate driving part sequentially applies a gate signal to the n-th gate line and the (n+1)-th gate line.

Abstract: A display device includes a driving device, which includes a signal controller which receives an input image signal and an input control signal and outputs an image data and a data control signal; a reference voltage generator which generates a first reference voltage and a second reference voltage; and a data driver which receives the image data and the data control signal from the signal controller and outputs a data voltage. The data control signal includes a first color gamma control signal, a second color gamma control signal, and a third color gamma control signal. The data driver includes a reference gamma voltage generator which receives the first reference voltage and the second reference voltage from the reference voltage generator, receives the first color, second color, and third color gamma control signals from the signal controller, and generates a reference gamma voltage according to color information of the image data.

Abstract: In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Abstract: A driving apparatus of a display device includes: a panel driving unit that receives a panel control signal and a first light control signal from an external device, drives a display panel of the display device based on the panel control signal, processes the first light control signal, and outputs the processed first light control signal as a second light control signal; and a light driving unit that drives the light source based on the second light control signal, where the second light control signal is configured to have the light source provide light for the display panel after a completion of a pre-display operation of the panel driving unit.

Abstract: Provided is a method of recycling waste scagliola, which includes a pre-treating step, a pyrolysing step, a resin recycling step, and a filler recycling step. The pre-treating step includes storing the waste scagliola of a dry dust type, drying and storing the waste scagliola of a wet dust type, or pulverizing and storing the waste scagliola of a scrap type. The pyrolysing step includes receiving and heating a recycling raw material stored in the dust or granular type in the pre-treating step, and decomposing the raw material into a resin mixed gas and a filler mixed solid material. The resin recycling step includes receiving the resin mixed gas decomposed in the pyrolysing step, and recycling a resin from which impurities are removed by a purifying process. The filler recycling step includes receiving the filler mixed solid material decomposed in the pyrolysing step, and recycling a filler from which impurities are removed by a firing process.

Abstract: A gate driving circuit that may be capable of improving driving margin and maintaining reliability even after long use, and a display device having the gate driving circuit. The gate driving circuit includes a shift register having a plurality of stages dependently connected to one another, wherein each stage includes a pull-up unit outputting a first clock signal as a gate signal in response to a signal of a first node, to which a first input signal is applied, a pull-down unit discharging the gate signal to a gate-off voltage in response to a second input signal, a discharging unit discharging the signal of the first node to the gate-off voltage in response to the second input signal, and a holding unit maintaining the signal of the first node at the gate-off voltage in response to a delay signal of the first clock signal.

Abstract: A display device includes a driving device, which includes a signal controller which receives an input image signal and an input control signal and outputs an image data and a data control signal; a reference voltage generator which generates a first reference voltage and a second reference voltage; and a data driver which receives the image data and the data control signal from the signal controller and outputs a data voltage. The data control signal includes a first color gamma control signal, a second color gamma control signal, and a third color gamma control signal. The data driver includes a reference gamma voltage generator which receives the first reference voltage and the second reference voltage from the reference voltage generator, receives the first color, second color, and third color gamma control signals from the signal controller, and generates a reference gamma voltage according to color information of the image data.

Abstract: A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.

Abstract: A data processing method for a display apparatus includes comparing data signals outputted to a first data line and a second data line of a plurality of data lines of a data driving circuit in the display apparatus to generate an output buffer control signal, and outputting output signals from at least one amplifier of a plurality of amplifiers of an output buffer in the data driving circuit to the first data line and the second data line, where the at least one amplifier is selected based on the output buffer control signal.

Abstract: A display panel includes a plurality of data lines, a plurality of gate lines, a plurality of dummy loads, a pad portion and a fanout portion. The data lines are disposed in a display area, on which a plurality of pixels are disposed. The gate lines are disposed in the display area and cross the data lines. The dummy loads are disposed in a peripheral area surrounding the display area. The pad portion is disposed in the peripheral area and includes signal pads and dummy pads. The fanout portion includes a first fanout line portion connecting the data lines to the signal pads, and a second fanout line portion connecting the dummy loads to the dummy pads.

Abstract: A power supply apparatus includes a storage battery, a power part and a solar battery part. The storage battery provides a charged voltage to an electronic device. The power part provides an external voltage to the electronic device and simultaneously charges the storage battery, upon determining that the external voltage is provided to the power supply apparatus. The solar battery part charges the storage battery using a voltage output by a solar battery upon determining that the external voltage is not provided to the power supply apparatus and the electronic device is not in use, and provides the voltage output by the solar battery and the charged voltage output by the storage battery to the electronic device, upon determining that the external voltage is not provided to the power supply apparatus and the electronic device is in use.

Abstract: A display device including a plurality of pixel electrodes arranged in a matrix including rows and columns and a plurality switching elements coupled with the pixel electrodes; a plurality of gate lines coupled with the switching elements and extending in a row direction, at least two gate lines assigned to a row; and a plurality of data lines coupled with the switching elements and extending in a column direction, a data line assigned to at least two columns, wherein each of the pixel electrodes has a first side and a second side that is farther from a data line than the first side, and the switching elements are disposed near the second sides of the pixel electrodes.

Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

Abstract: A display apparatus includes a display panel and a data driving part. The display panel includes pixels, data lines and gate lines. A transverse side of the pixels is disposed adjacent to the data lines extending along a first direction, and a longitudinal side of the pixels is disposed adjacent to the gate lines extending along a second direction. Two adjacent pixels of the pixels disposed adjacent to each other along the second direction are connected to one gate line of the gate lines. The data driving part transmits two-dot-inversed first direction data voltages to pixels disposed along the second direction and two-dot-inversed second direction data voltages to pixels disposed along the first direction.

Abstract: A transistor includes a control electrode, a first current electrode and a second current electrode. The control electrode includes a body portion, and first and second hand portions protruded from first and second ends of the body portion, respectively. The first current electrode is electrically insulated from the control electrode and disposed over a region between the first and second hand portions of the control electrode. A portion of the first current electrode is overlapped with a portion of the control electrode. The second current electrode is electrically insulated from the control electrode and partially overlapped with the body portion, the first hand portion and the second hand portion of the control electrode. Therefore, parasitic capacitance is reduced.

Abstract: A display device includes a display panel, a data driving part and a gate driving part. The display panel includes a first pixel row. The first pixel row includes a first pixel connected to an (n+1)-th gate line and an (m+1)-th data line (where ‘n’ and ‘m’ are natural numbers), and a second pixel connected to an n-th gate line and an (m+2)-th data line. The data driving part applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line, and applies a data voltage having a second polarity with respect to the reference voltage to the (m+2)-th data line. The gate driving part sequentially applies a gate signal to the n-th gate line and the (n+1)-th gate line.

Abstract: A display device that employs fewer IC chips and lends itself to cost-efficient manufacturing is presented. The device includes: a plurality of pixel rows including first and second pixels alternately arranged; a plurality of first and second gate lines disposed above and below the pixel rows and applying first and second gate-on voltages to the first and the second pixels, respectively; data lines intersecting the first and the second gate lines, each data line disposed between the first and the second pixels in a pair of first and second pixels and applying data voltages to the first and the second pixels; first and second gate drivers applying the first and the second gate-on voltages to the first and the second gate lines; and a data driver applying the data voltages to the data lines, wherein the second gate-on voltage is applied earlier than the first gate-on voltages by a predetermined time.

Abstract: A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.

Abstract: Gate-driving circuitry of a thin film transistor array panel is formed on the same plane as a display area of the transistor array panel. The gate-driving circuitry includes driving circuitry and signal lines having apertures. Thus, a sufficient amount of light, even though illuminated from the thin film transistor array panel side, can reach a photosetting sealant overlapping at least in part the gate-driving circuitry. The thin film transistor array panel and the counter panel are put together air-tight and moisture-tight. Consequently, the gate-driving circuitry can avoid corrosion by moisture introduced from outside. Gate-driving circuitry malfunctions can also be reduced.