Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.

Abstract: The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate.

Abstract: The present invention provides a method for implanting ions in a semiconductor device capable of compensating for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate and another method for fabricating a semiconductor device capable of improving distribution of transistor parameters inside a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile.

Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.

Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.

Abstract: The method for forming a flowable dielectric layer without micro-voids therein in a semiconductor device is employed to utilize a ultra-violet (UV) bake process. The method includes steps of: forming a plurality of patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out a baking process for densifying the flowable dielectric layer from a bottom face thereof; forming a plurality of contact holes by selectively etching the flowable dielectric layer; carrying out a pre-cleaning process in order to remove native oxide and impurity substances on the contact holes; and forming a plurality of contact plugs by filling a conductive material into the contact holes.

Abstract: The present invention provides a method for implanting ions in a semiconductor device capable of compensating for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate and another method for fabricating a semiconductor device capable of improving distribution of transistor parameters inside a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile.

Abstract: The method for manufacturing an STI in a semiconductor device with an enhanced gap-fill property and leakage property is disclosed by introducing a nitridation process instead of forming a liner nitride. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming an isolation trench with a predetermined depth in the semiconductor substrate; forming a wall oxide on the trench; forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; carrying out a nitridation process for forming a nitrided oxide; forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and planarizing a top face of the insulating layer.

Abstract: The present invention provides a manufacturing method of a contact for use in a semiconductor device and a manufacturing method of a PMOS device using the same, which can obtain an electrical characteristic of a low contact resistance similar to a mixed implantation of 49BF2+ ions and 11B+ ions and reduce a manufacturing cost. The method for forming a contact of a semiconductor device includes: the steps of: forming an insulating layer on a conductive semiconductor layer; forming a contact hole within the insulating layer to expose a portion of the conductive semiconductor layer; forming a plug implantation region by implanting 30BF+ ions into the exposed conductive semiconductor layer disposed on a bottom of the contact hole; performing an annealing process for activating dopants injected by the implantation of 30BF+ ions; and filling the contact hole with a conductive layer.

Abstract: The present invention provides a p-channel metal-oxide-semiconductor (pMOS) device having an ultra shallow epi-channel satisfying a high doping concentration required for a device of which gate length is about 30 nm even without using a HALO doping layer and a method for fabricating the same. The pMOS device includes: a semiconductor substrate; a channel doping layer being formed in a surface of the semiconductor substrate and being dually doped with dopants having different diffusion rates; a silicon epi-layer being formed on the channel doping layer, whereby constructing an epi-channel along with the channel doping layer; a gate insulating layer formed on the silicon epi-layer; a gate electrode formed on the gate insulating layer; a source/drain extension region highly concentrated and formed in the semiconductor substrate of lateral sides of the epi-channel; and a source/drain region electrically connected to the source/drain extension region and deeper than the source/drain region.

Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

Abstract: The method for manufacturing an STI in a semiconductor device with an enhanced gap-fill property and leakage property is disclosed by introducing a nitridation process instead of forming a liner nitride. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming an isolation trench with a predetermined depth in the semiconductor substrate; forming a wall oxide on the trench; forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; carrying out a nitridation process for forming a nitrided oxide; forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and planarizing a top face of the insulating layer.

Abstract: The method for forming a flowable dielectric layer without micro-voids therein in a semiconductor device is employed to utilize a ultra-violet (UV) bake process. The method includes steps of: forming a plurality of patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out a baking process for densifying the flowable dielectric layer from a bottom face thereof; forming a plurality of contact holes by selectively etching the flowable dielectric layer; carrying out a pre-cleaning process in order to remove native oxide and impurity substances on the contact holes; and forming a plurality of contact plugs by filling a conductive material into the contact holes.

Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

Abstract: The present invention provides a p-channel metal-oxide-semiconductor (pMOS) device having an ultra shallow epi-channel satisfying a high doping concentration required for a device of which gate length is about 30 nm even without using a HALO doping layer and a method for fabricating the same. The pMOS device includes: a semiconductor substrate; a channel doping layer being formed in a surface of the semiconductor substrate and being dually doped with dopants having different diffusion rates; a silicon epi-layer being formed on the channel doping layer, whereby constructing an epi-channel along with the channel doping layer; a gate insulating layer formed on the silicon epi-layer; a gate electrode formed on the gate insulating layer; a source/drain extension region highly concentrated and formed in the semiconductor substrate of lateral sides of the epi-channel; and a source/drain region electrically connected to the source/drain extension region and deeper than the source/drain region.

Abstract: The present invention provides a method for fabricating a semiconductor device with ultra-shallow super-steep-retrograde epi-channel that is able to overcome limitedly useable energies and to enhance manufacturing productivity than using ultra low energy ion implantation technique that has disadvantage of difficulties to get the enough ion beam current as well as that of prolonged processing time.

Abstract: This invention relates to a method for fabricating a semiconductor device with the epi-channel structure, which is adapted to overcome an available energy limitation and to improve the productivity by providing the method of SSR epi Channel doping by boron-fluoride compound ion implantation without using ultra low energy ion implantation and a method for fabricating the semiconductive device with epi-channel structure adapted to prevent the crystal defects caused by the epitaxial growth on ion bombarded and fluorinated channel doping layer.

Abstract: The present invention provides a manufacturing method of a contact for use in a semiconductor device and a manufacturing method of a PMOS device using the same, which can obtain an electrical characteristic of a low contact resistance similar to a mixed implantation of 49BF2+ ions and 11B+ ions and reduce a manufacturing cost. The method for forming a contact of a semiconductor device includes: the steps of: forming an insulating layer on a conductive semiconductor layer; forming a contact hole within the insulating layer to expose a portion of the conductive semiconductor layer; forming a plug implantation region by implanting 30BF+ ions into the exposed conductive semiconductor layer disposed on a bottom of the contact hole; performing an annealing process for activating dopants injected by the implantation of 30BF+ ions; and filling the contact hole with a conductive layer.

Abstract: This invention relates to a method for fabricating a semiconductor device with the epi-channel structure, which is adapted to overcome an available energy limitation and to improve the productivity by providing the method of SSR epi Channel doping by boron-fluoride compound ion implantation without using ultra low energy ion implantation and a method for fabricating the semiconductive device with epi-channel structure adapted to prevent the crystal defects caused by the epitaxial growth on ion bombarded and fluorinated channel doping layer.