Patents by Inventor Yong-surk Lee

Yong-surk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9292458
    Abstract: A method of performing collective communication in a collective communication system includes processing nodes, including: determining whether a command message, regarding one function among a broadcast function, a scatter function, and a gather function, is generated by a processor; determining a transmission order between the processing nodes by giving transmission priorities to processing nodes that do not communicate, based on a status of each of the processing nodes if it is determined that the command message regarding the one function among the broadcast function, the scatter function, and the gather function, is generated by the processor; and performing communication with respect to the command message based on the determined transmission order.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 22, 2016
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Won-young Chung, Yong Surk Lee, Jong-su Park, Ha-young Jeong
  • Patent number: 8874630
    Abstract: An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: October 28, 2014
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyeong-Seok Yu, Suk-Jin Kim, Sang-Su Park, Yong-Surk Lee
  • Patent number: 8805915
    Abstract: A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: August 12, 2014
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyeong-Seok Yu, Dong-Kwan Suh, Suk-Jin Kim, San Kim, Yong-Surk Lee
  • Publication number: 20140156890
    Abstract: A method of performing collective communication in a collective communication system includes processing nodes, including: determining whether a command message, regarding one function among a broadcast function, a scatter function, and a gather function, is generated by a processor; determining a transmission order between the processing nodes by giving transmission priorities to processing nodes that do not communicate, based on a status of each of the processing nodes if it is determined that the command message regarding the one function among the broadcast function, the scatter function, and the gather function, is generated by the processor; and performing communication with respect to the command message based on the determined transmission order.
    Type: Application
    Filed: February 27, 2013
    Publication date: June 5, 2014
    Applicants: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-young CHUNG, Yong Surk LEE, Jong-su PARK, Ha-young JEONG
  • Publication number: 20120124117
    Abstract: A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.
    Type: Application
    Filed: June 6, 2011
    Publication date: May 17, 2012
    Inventors: Hyeong-Seok Yu, Dong-Kwan Suh, Suk-Jin Kim, San Kim, Yong-Surk Lee
  • Publication number: 20120124116
    Abstract: An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.
    Type: Application
    Filed: May 5, 2011
    Publication date: May 17, 2012
    Inventors: Hyeong-Seok YU, Suk-Jin Kim, Sang-Su Park, Yong-Surk Lee
  • Publication number: 20060095733
    Abstract: A hardware device for executing conditional instructions out-of-order and the execution method. An architecture is provided, enabling the hardware device such as a processor supporting the conditional instruction and a computer system to execute the instruction out-of-order. To this end, a conditional execution buffer is provided, and a register of a destination operand of the conditional instruction is renamed to another register. Hence, the hardware device using the conditional instruction can carry out the out-of-order execution, and the execution speed of the hardware device can be greatly improved.
    Type: Application
    Filed: September 7, 2005
    Publication date: May 4, 2006
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-surk Lee, Ha-young Jeong, Nam-guk Kim, Jin-oo Joung, Tae-ho Jang, Dae-ung Kim