Abstract: A video encoding/decoding apparatus according to the present invention acquires motion vector refinement information, performs motion compensation on the basis of a motion vector of a current block, refines the motion vector of the current block using at least one or both of the motion vector refinement information and the output of the motion compensation, and performs motion compensation using the refined motion vector.

Abstract: The inventive concept provides a substrate treating method. The substrate treating method includes taking in a substrate to a treating space to mount on a support unit; upwardly moving the support unit after mounting the substrate on the support unit; determining whether the support unit moves normally after the upwardly moving the support unit; and treating the substrate by generating a plasma in the treating space, and wherein at the determining whether the support unit moves normally, before the plasma is generated at the treating space at the treating the substrate, whether a pulse distance matching a predetermined distance data according to a pulse value of a driving unit which pulse-moves a moving body which moves the support unit in a top/down direction, matches a movement distance of the moving body is determined, and an interlock is generated if the pulse distance and the movement distance is different.

Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.

Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.

Abstract: A method of fabricating a semiconductor device includes forming a conductive layer on a semiconductor substrate, forming an insulating layer on the conductive layer, forming a word line and isolation trenches by patterning the insulating layer and the conductive layer, forming an isolation layer that fills the isolation trenches, forming a cell contact hole in the insulating layer such that the cell contact hole is self-aligned with the word line and exposes the word line, and forming a cell diode in the cell contact hole.

Abstract: Semiconductor memory devices having strapping contacts with an increased pitch are provided. The semiconductor memory devices include cell regions and strapping regions between adjacent cell regions in a first direction on a semiconductor substrate. Active patterns extend in the first direction throughout the cell regions and strapping regions and are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines extend in the first direction throughout the cell regions and the strapping regions and are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines extend in the second direction to intersect the active patterns and the first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.

Abstract: Provided are a method of forming a metal layer wiring structure on the backside of a wafer, a metal layer wiring structure formed using the method, a method of stacking a chip package, and a chip package stack structure formed using the method. The method of stacking a chip package includes: forming recess patterns on a backside of wafers; forming a passivation layer on the backside of the wafers except for an area corresponding to a through electrode; forming a metal layer on the passivation layer; planarizing the metal layers to expose only the recess patterns; forming a lower insulating layer on the planarized metal layers except for an area corresponding to a contact portion with another wafer; forming an adhesive layer on the lower insulating layer of each of the wafers; and adhering the wafers to one another, wherein the recess patterns are formed using a laser.

Abstract: A method of fabricating a semiconductor device includes forming a conductive layer on a semiconductor substrate, forming an insulating layer on the conductive layer, forming a word line and isolation trenches by patterning the insulating layer and the conductive layer, forming an isolation layer that fills the isolation trenches, forming a cell contact hole in the insulating layer such that the cell contact hole is self-aligned with the word line and exposes the word line, and forming a cell diode in the cell contact hole.