Patents by Inventor Yong-Tae Yim
Yong-Tae Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9251015Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.Type: GrantFiled: May 9, 2014Date of Patent: February 2, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Tae Yim, Sung-Kue Jo
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Patent number: 9229805Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.Type: GrantFiled: September 4, 2008Date of Patent: January 5, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Tae Yim, Sung-Kue Jo
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Patent number: 8898543Abstract: Disclosed are program and read methods for a nonvolatile memory system, including determining to program first data in which one of fast and normal modes; providing the first data with an error code generated by a multi-bit ECC engine, in the fast mode, and generating second data; programming the second data in a cell array by a program voltage having a second start level higher than a first start level; and reading the second data from the cell array, the second data being output after processed by the multi-bit ECC engine that detects and corrects an error from the second data.Type: GrantFiled: August 13, 2008Date of Patent: November 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Kyu Jo, Yong-Tae Yim
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Publication number: 20140245109Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.Type: ApplicationFiled: May 9, 2014Publication date: August 28, 2014Inventors: Yong-Tae YIM, Sung-Kue JO
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Patent number: 8726140Abstract: A data processing method of a memory controller includes receiving first partial data of a last sector data among a plurality of sector data to be stored in an n-th page of a non-volatile memory in a program operation; padding the first partial data with first dummy data and generating a first error correction code (ECC) parity in the program operation; and transferring the first partial data and the first ECC parity to the non-volatile memory in the program operation, while refraining from transferring the first dummy data to the non-volatile memory. Related devices and systems are also described.Type: GrantFiled: April 4, 2012Date of Patent: May 13, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Tae Chang, Yong Tae Yim
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Patent number: 8522114Abstract: A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.Type: GrantFiled: April 27, 2010Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Woo tae Chang, Yong tae Yim
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Publication number: 20120260149Abstract: A data processing method of a memory controller includes receiving first partial data of a last sector data among a plurality of sector data to be stored in an n-th page of a non-volatile memory in a program operation; padding the first partial data with first dummy data and generating a first error correction code (ECC) parity in the program operation; and transferring the first partial data and the first ECC parity to the non-volatile memory in the program operation, while refraining from transferring the first dummy data to the non-volatile memory. Related devices and systems are also described.Type: ApplicationFiled: April 4, 2012Publication date: October 11, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Woo Tae Chang, Yong Tae Yim
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Publication number: 20120072810Abstract: An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.Type: ApplicationFiled: September 22, 2011Publication date: March 22, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Tae YIM, Yun-Ho CHOI
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Patent number: 8091010Abstract: An error correction circuit and method for reducing a miscorrection probability and a semiconductor memory device including the circuit are provided. The error correction circuit includes an error check and correction (ECC) encoder and an ECC decoder. The ECC encoder generates syndrome data enabling h-bit error correction based on information data and a generator polynomial, where “h” is 2 or an integer greater than 2. The ECC decoder may operate in a single mode for detecting an error position with respect to a maximum of (h?j) bits in the information data based on encoded data including the information and the syndrome data, where “j” is 1 or an integer greater than 1.Type: GrantFiled: August 7, 2007Date of Patent: January 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Yong-Tae Yim
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Publication number: 20110296131Abstract: A memory controller includes a microprocessor, a queue configured to store a plurality of first commands provided by the microprocessor, a queue management block configured to interpret and control said plurality of first commands, and a command generator configured to provide a plurality of second commands under control of the queue management block. The queue management block may simultaneously perform the plurality of second commands so as to simultaneously access a plurality of non-volatile memory units.Type: ApplicationFiled: May 27, 2011Publication date: December 1, 2011Applicant: Samsung Electronics Co., LtdInventors: Yong Tae YIM, Won Moon CHEON, Jin Yeong KIM, Du-Won HONG, Jong-Min KIM
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Patent number: 8069389Abstract: An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.Type: GrantFiled: July 12, 2007Date of Patent: November 29, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Tae Yim, Yun-Ho Choi
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Publication number: 20100281342Abstract: A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.Type: ApplicationFiled: April 27, 2010Publication date: November 4, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo tae CHANG, Yong tae YIM
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Publication number: 20090077429Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.Type: ApplicationFiled: September 4, 2008Publication date: March 19, 2009Inventors: Yong-Tae Yim, Sung-Kue Jo
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Publication number: 20090049364Abstract: Disclosed are program and read methods for a nonvolatile memory system, including determining to program first data in which one of fast and normal modes; providing the first data with an error code generated by a multi-bit ECC engine, in the fast mode, and generating second data; programming the second data in a cell array by a program voltage having a second start level higher than a first start level; and reading the second data from the cell array, the second data being output after processed by the multi-bit ECC engine that detects and corrects an error from the second data.Type: ApplicationFiled: August 13, 2008Publication date: February 19, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Kyu JO, Yong-Tae YIM
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Publication number: 20080163033Abstract: An error correction circuit and method for reducing a miscorrection probability and a semiconductor memory device including the circuit are provided. The error correction circuit includes an error check and correction (ECC) encoder and an ECC decoder. The ECC encoder generates syndrome data enabling h-bit error correction based on information data and a generator polynomial, where “h” is 2 or an integer greater than 2. The ECC decoder may operate in a single mode for detecting an error position with respect to a maximum of (h?j) bits in the information data based on encoded data including the information and the syndrome data, where “j” is 1 or an integer greater than 1.Type: ApplicationFiled: August 7, 2007Publication date: July 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yong-Tae YIM
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Publication number: 20080052564Abstract: An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.Type: ApplicationFiled: July 12, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Tae YIM, Yun-Ho CHOI