Abstract: A medium composition for inducing differentiation of taste bud organoids derived from the anterior tongue epithelium, a method for producing taste bud organoids, a taste bud organoid derived from the anterior tongue epithelium, and a method for screening a tastant using the same, wherein the medium composition for inducing differentiation of taste bud organoids derived from the anterior tongue epithelium and the method for producing taste bud organoids using the same may efficiently form the taste bud organoids from tongue epithelial tissue and may control their differentiation into specific types of taste cells. In addition, the taste bud organoids derived from the anterior tongue epithelium formed by the method may maximize the expression of markers for various taste buds and cells that make up taste buds to express salty taste detection proteins, so that they may be used in various fields such as cell sensors and tastant screening.

Abstract: A server device includes a plurality of interface circuits configured to connect with a network, and perform format conversion between network packets and data chunks, the network packets being packets communicated with the network, the data chunks complying with an internal format; a plurality of memory modules operating independently of each other; and a switch circuit connected between the plurality of interface circuits and the plurality of memory modules, the switch circuit being configured to select at least one memory module from among the plurality of memory modules based on an attribute of a first data chunk transmitted from the plurality of interface circuits and, send the first data chunk to the selected memory module, wherein the selected at least one memory module is configured to, decode the first data chunk, and perform a read or write operation associated with the first data chunk based on the decoding result.

Abstract: An object storage system includes a plurality of memory devices; and a memory controller configured to, receive a value and a key from a host, the key identifying the received value, store data corresponding to the received value in the plurality of memory devices, generate, based on the received value, a parity for detecting an error of the stored data, manage key-value mapping information that identifies a correspondence relationship between the received value and the key, and manage the parity in the key-value mapping information such that the parity corresponds to the received value and the key.

Abstract: An operation method of a data storage system including storage devices includes transmitting a packet to a host including information indicating whether the storage devices are capable of resource sharing; transmitting ID information of the storage devices capable of resource to the host; transmitting by a requesting device among the capable storage devices a resource sharing request message to the remaining storage devices capable of resource sharing; and performing the resource sharing on at least one of the remaining storage devices.

Abstract: An object storage system includes a plurality of memory devices; and a memory controller configured to, receive a value and a key from a host, the key identifying the received value, store data corresponding to the received value in the plurality of memory devices, generate, based on the received value, a parity for detecting an error of the stored data, manage key-value mapping information that identifies a correspondence relationship between the received value and the key, and manage the parity in the key-value mapping information such that the parity corresponds to the received value and the key.

Abstract: A server device includes a plurality of interface circuits configured to connect with a network, and perform format conversion between network packets and data chunks, the network packets being packets communicated with the network, the data chunks complying with an internal format; a plurality of memory modules operating independently of each other; and a switch circuit connected between the plurality of interface circuits and the plurality of memory modules, the switch circuit being configured to select at least one memory module from among the plurality of memory modules based on an attribute of a first data chunk transmitted from the plurality of interface circuits and, send the first data chunk to the selected memory module, wherein the selected at least one memory module is configured to, decode the first data chunk, and perform a read or write operation associated with the first data chunk based on the decoding result.

Abstract: An operation method of a data storage system including storage devices includes transmitting a packet to a host including information indicating whether the storage devices are capable of resource sharing; transmitting ID information of the storage devices capable of resource to the host; transmitting by a requesting device among the capable storage devices a resource sharing request message to the remaining storage devices capable of resource sharing; and performing the resource sharing on at least one of the remaining storage devices.

Abstract: A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.

Abstract: Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command. It is determined if the first address of the page of data is the same as a stored address of the page at which the failure was detected. The first address is incremented if it is determined that the first address and the stored address are not the same. The pages of data are replaced, the addressed are compared and the addresses are incremented until it is determined that the incremented address and the stored address are the same. Related devices and systems are also provided herein.

Abstract: A flash memory device may include a pump, a regulator to control the pump so that an output voltage of the pump is substantially maintained at a target voltage, and a control circuit to control the regulator so that the pump selectively generates a program voltage or an erase voltage. In some embodiments, the output voltage of the pump may be stepped in response to program loop iterations during a program operation, or set to a target voltage during an erase operation.

Abstract: A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.

Abstract: Embodiments of the invention provide a high voltage transfer circuit, a row decoder circuit comprising the high voltage transfer circuit, and a non-volatile semiconductor memory device comprising the high voltage transfer circuit. In one embodiment, the invention provides a high voltage transfer circuit of a semiconductor memory device comprising a high voltage switch comprising a high voltage transistor comprising a first terminal connected to a boosted voltage via a first depletion-type transistor and comprising a second terminal connected to an output node via a second depletion-type transistor. The high voltage transfer circuit further comprises a driver circuit adapted to drive the first and second depletion-type transistors and the high voltage transistor in response to an input signal.

Abstract: A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read write and/or erase data.

Abstract: A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read right and/or erase data.

Abstract: Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command. It is determined if the first address of the page of data is the same as a stored address of the page at which the failure was detected. The first address is incremented if it is determined that the first address and the stored address are not the same. The pages of data are replaced, the addressed are compared and the addresses are incremented until it is determined that the incremented address and the stored address are the same. Related devices and systems are also provided herein.

Abstract: Embodiments of the invention provide a high voltage transfer circuit, a row decoder circuit comprising the high voltage transfer circuit, and a non-volatile semiconductor memory device comprising the high voltage transfer circuit. In one embodiment, the invention provides a high voltage transfer circuit of a semiconductor memory device comprising a high voltage switch comprising a high voltage transistor comprising a first terminal connected to a boosted voltage via a first depletion-type transistor and comprising a second terminal connected to an output node via a second depletion-type transistor. The high voltage transfer circuit further comprises a driver circuit adapted to drive the first and second depletion-type transistors and the high voltage transistor in response to an input signal.

Abstract: Disclosed is a page buffer for a nonvolatile semiconductor memory device and a related method of operation. The page buffer includes a unidirectional driver between a loading latch unit used for storing a data bit in the page buffer and a bitline used to program a memory cell connected to the page buffer.

Abstract: A flash memory device may include a pump, a regulator to control the pump so that an output voltage of the pump is substantially maintained at a target voltage, and a control circuit to control the regulator so that the pump selectively generates a program voltage or an erase voltage. In some embodiments, the output voltage of the pump may be stepped in response to program loop iterations during a program operation, or set to a target voltage during an erase operation.

Abstract: Disclosed is a page buffer for a nonvolatile semiconductor memory device and a related method of operation. The page buffer includes a unidirectional driver between a loading latch unit used for storing a data bit in the page buffer and a bitline used to program a memory cell connected to the page buffer.