Abstract: An address transition detection circuit for a memory device, by which an address transition detect signal having a pulse width required for operating the memory device is outputted regardless of a pulse width of an address signal inputted to the memory device to thereby prevent any malfunction of the memory device, includes a NOR gate for NORing the inputted address signal and a chip select signal; a latch for latching an output signal of the NOR gate by first to third input delay signals to output first and second latch signals; first and second signal delays for respectively delaying the first and second latch signals provided from the latch for a predetermined time to respectively output first and second delay signals; and a signal output unit for outputting the address transition detect signal in accordance with the first and second latch signals respectively provided from the latch and the first and second delay signals respectively provided from the first and second signal delays.

Abstract: A word line supply circuit reducing the capacitance operating as a load at a time of enabling a word line in a semiconductor memory, resulting in the internal voltage supply being more stable. A word line voltage supply circuit is provided for directly driving the word line by the internal voltage supply Vpp and whereby pulling up the word line to the Vpp level. A row decoder 100 receives a voltage from a Vcc power supply and receives an address signal and outputs an RDout signal that selects a predetermined number of a word line group. A reset level converter 200 receives a voltage from a Vpp power supply which is a higher voltage level than Vcc, and receives the RDout signal and a RESET signal for resetting the word line and outputs a RESET signal. A word line driver controller 300 receives a voltage from the Vpp power supply and receives the RDout signal, RESET signal and a pre-decoder signal as inputs and outputs a WLEN signal, which is a word line control signal.