Abstract: A liquid crystal display device includes a transparent substrate, a gate electrode disposed on the transparent substrate, a gate insulating film disposed on the transparent substrate and covering the gate electrode, an active layer disposed on the gate insulating film, an ohmic contact layer disposed on the active layer, a source electrode disposed on the ohmic contact layer and at one side of the gate electrode, a drain electrode disposed on the ohmic contact layer and at another side of the gate electrode, the drain electrode including an L-shaped portion and a plurality of protrusions, a protective layer disposed on the active layer covering upper surfaces of the source electrode and the drain electrode, and a pixel electrode disposed on the protective layer and electrically contacting a side surface of the drain electrode.

Abstract: The present invention discloses an array substrate for an active-matrix LCD device and a method of fabricating the same. The array substrate reduces the number of masks typically used in the fabrication process so that reliability is enhanced and the cost is reduced over the conventional device and method. Electric shorts caused by hillocks can be prevented or reduced by incorporating short-preventing sections between the gate line and an overlapping pixel electrode.

Abstract: An array substrate for use in a liquid crystal display device is fabricated by the steps of forming a first metal layer on a substrate, patterning the first metal layer to form a gate line, a gate electrode, a gate pad, a first shorting bar, and a second shorting bar, forming a gate insulation layer, a pure amorphous silicon layer, a doped amorphous silicon layer and a second metal layer to cover the patterned first metal layer, patterning the second metal layer and the doped amorphous silicon layer to form first, second and third through-holes and first and second grooves to expose a portion of the pure amorphous silicon layer, the first and second grooves creating an isolated portions of the second metal layer, forming a passivation layer to cover the patterned second metal layer, forming a source electrode, a drain electrode, a data line, a data pad, an insulating segment, and first, second and third contact holes, and forming a pixel electrode, a first connector and a second connector of a transparent con

Abstract: An electrostatic damage preventing apparatus for a thin film transistor array of a liquid crystal display includes a horizontal ground voltage line disposed at a first perimeter portion of the thin film transistor array, a vertical ground voltage line disposed at a second perimeter portion of the thin film transistor array, and a first electrostatic damage-preventing switching device group including parallel connection of at least two electrostatic damage-preventing switching devices to divide and divert an electrostatic voltage applied over the horizontal ground voltage line.

Abstract: A field emission array adopting carbon nanotubes as an electron emitter source and a method for fabricating same, wherein the fabrication method includes forming a rear substrate assembly including cathodes formed as stripes over a rear substrate, and carbon nanotubes; forming a front substrate assembly including anodes formed as stripes over a front substrate; depositing phosphors on the anodes; forming a plurality of openings separated by a predetermined distance in a nonconductive plate, corresponding to the anodes, and forming gates as stripes perpendicular to the stripes of anodes on the nonconductive plate with a plurality of emitter openings corresponding to the plurality of openings; supporting and separating the nonconductive plate from the rear substrate by a predetermined distance, using spacers; combining the rear substrate assembly with the front substrate assembly so the carbon nanotubes on the cathodes project through the emitter openings at a predetermined distance from the gates.

Abstract: A 4-mask method of manufacturing an array substrate. First and second masks form a gate line, a gate pad, a data line and a data pad. The data line has a protrusion near a crossing of the gate and data lines. A third mask forms a transparent electrode layer, a source electrode, a drain electrode, a pixel electrode, and exposes channel area. The transparent electrode layer has a similar shape as the data line and the data pad, but a smaller area than the data line and a greater area than the data pad. A second insulating layer is formed over the structure. A fourth mask patterns the second insulating layer to cover the gate line and the gate pad, the first and second insulating layer are patterned to form a gate pad contact hole, and the first insulating layer between the data line and the pixel electrode is patterned.

Abstract: A liquid crystal display is provided that includes a first substrate including a thin film transistor and a storage capacitor, a second substrate including a color filter layer with a recess at a location opposite to the storage capacitor, a common electrode on the color filter layer, and a liquid crystal layer between the first and second substrates. Spacers are provided between the first and second substrates to maintain a gap therebetween. In regions that include the storage capacitor, the recess compensates for a height difference in layers forming the capacitor on the first substrate to maintain a substantially uniform liquid crystal layer thickness over the whole region of the liquid crystal display, and thus provides a high quality picture.

Abstract: A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer). The over-etched portion also enables the aperture ratio to increase.

Abstract: A liquid crystal display device and a fabricating method thereof wherein four masks are used so as to reduce a process. In the device, a gate electrode is formed on a transparent substrate. A gate insulating film is formed on the transparent substrate to cover the gate electrode. An active layer is provided at a portion corresponding to the gate electrode on the gate insulating film. Source and drain electrodes are intervened by an ohmic contact layer on the active layer. A contact portion is connected to and extended from a portion of the drain electrode opposed to the source electrode and has an exposed side surface. A passivation layer is formed on the active layer in such a manner to cover the source and drain electrodes, but to expose the side surface of the contact portion. A pixel electrode is formed on the gate insulating film in such a manner to contact the exposed side surface of the contact portion.

Abstract: A liquid crystal display device includes dummy patterns formed between gate links and between data links. The gate links and data links are coated with a sealant to obtain the same height as a liquid crystal area at the opposite side thereof through the dummy patterns, providing a uniform cell gap.

Abstract: A yttrium silicate based phosphor with excellent luminescent efficiency at low voltages for utility in field emission devices (FEDs), and a method for synthesizing the phosphor. The yttrium silicate based phosphor contains Eu, Ce or Tb as an activator, phosphorus as a flux, and Zn as a sensitizer, based on a yttrium silicate phosphor, for example, Y3SiO5:Tb phosphor, and thus the luminance is improved.

Abstract: A red phosphor having effective emission at low voltages, prepared using a conductive luminescent material, and a method for preparing the same, which is applicable in low-voltage driving image display displays such as field emission displays (FEDs) with improved luminance. By coating the surface of a red phosphor with the conductive luminescent material, accumulation of charges in FEDs can be prevented and thus the luminance is enhanced.

Abstract: The present invention discloses a method for accessing a cell, and more particularly, to a method for acquiring an initial synchronization using two pilot channels in a CDMA (Code Division Multiple Access) communication system of an asynchronous or quasi-synchronous mode. In accordance with the present invention, a CDMA communication system of an quasi-synchronous mode comprises the steps of synchronizing the mobile station with a cluster pilot, and searching for cell pilots on the basis of the cluster synchronization channel set up by the cluster pilot, and synchronizing the mobile station with the cell pilot having a maximum sensitivity, whereby the mobile station is synchronized with the base station through the cluster pilot and the cell pilot.

Abstract: A flash electrically erasable programmable read only memory (EEPROM) device includes a two-dimensional array of single transistor non-volatile memory cells having the mid channel injection mechanism. The single transistor non-volatile memory cell includes a select gate, a control gate, and a floating gate which are disposed above a channel between a source and a drain. The control gate is located above the floating gate. In order to program the memory cell, the carrier injection into the floating gate is accomplished by the deflection of accelerated carriers from the middle region of the channel. Carriers are accelerated through the carrier acceleration passage by the horizontal component of the stray electric field, and deflected by the vertical component of the electric field. The erasure of memory cell is accomplished by the tunneling of carriers from the floating gate to the drain.