Patents by Inventor Yong Wee, Francis POH

Yong Wee, Francis POH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194498
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Patent number: 10629650
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Publication number: 20200075668
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Application
    Filed: August 29, 2018
    Publication date: March 5, 2020
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Publication number: 20180182809
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, the integrated circuit includes a plurality of magnetic random access memory (MRAM) structures. Each of the MRAM structures includes a bottom electrode. The MRAM structures further include a magnetic tunnel junction stack (MTJ stack) overlying and in electrical communication with the bottom electrode. The MRAM structures also include a top electrode layer overlying and in electrical communication with the MTJ stack. The integrated circuit further includes a spin-on dielectric layer at least partially encapsulating the MRAM structures with the spin-on dielectric layer disposed between adjacent MRAM structures.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Hongxi Liu, Chenchen Jacob Wang, Yew Tuck Clament Chow, Narayanapillai Kulothungasagaran, Yong Wee Francis Poh, Jin Ho Lee, Jianbo Yang
  • Patent number: 9589616
    Abstract: Memory cell, method for operating the memory cell and method for fabricating the memory cell are disclosed. The memory cell includes at least three terminals, a first magnetic tunnel junction (MTJ) structure and a second MTJ structure. The first MTJ is coupled between a first terminal (FT) and a third terminal. A portion of the first MTJ is configured to include a first barrier layer disposed between a first fixed layer and a free layer (FL). A magnetization direction of the FL is used to store data, the magnetization direction being controlled by an electric field. The second MTJ is coupled between the FT and a second terminal, where a portion of the second MTJ is configured to include a second barrier layer disposed between a second fixed layer and the FL, where a tunnel magnetoresistance of the second barrier layer is used to read the data.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 7, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Hao Meng, Yong Wee Francis Poh, Tze Ho Simon Chan
  • Patent number: 9583167
    Abstract: Memory cell, method for operating the memory cell and method of forming the memory cell are disclosed. The memory cell includes a first selector having a first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, and a second selector having at least a second select transistor with a second gate coupled to a second wordline and first and second S/D regions. The memory cell includes a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D region of the first select transistor, and a second MTJ element coupled between a second bit line and the first S/D region of the second select transistor.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Tze Ho Simon Chan, Yang Hong, Yong Wee Francis Poh
  • Publication number: 20160322090
    Abstract: Memory cell, method for operating the memory cell and method of forming the memory cell are disclosed. The memory cell includes a first selector having a first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, and a second selector having at least a second select transistor with a second gate coupled to a second wordline and first and second S/D regions. The memory cell includes a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D region of the first select transistor, and a second MTJ element coupled between a second bit line and the first S/D region of the second select transistor.
    Type: Application
    Filed: April 29, 2015
    Publication date: November 3, 2016
    Inventors: Tze Ho Simon CHAN, Yang HONG, Yong Wee Francis POH
  • Patent number: 9406764
    Abstract: Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate prepared with an isolation well, a HV well region and first and second wells disposed in the substrate. The memory cell further includes a first transistor having a select gate and a second transistor having a floating gate adjacent to one another and disposed over the second well. The transistors include first and second diffusion regions disposed adjacent to the sides of the gates. A control gate is disposed over the first well and coupled to the floating gate. The control and floating gates include the same gate layer extending across the first and second wells. The control gate includes a capacitor.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Yong Wee Francis Poh, Upinder Singh, Yuan Sun, Myo Aung Maung Maung
  • Publication number: 20160125925
    Abstract: Memory cell, method for operating the memory cell and method for fabricating the memory cell are disclosed. The memory cell includes at least three terminals, a first magnetic tunnel junction (MTJ) structure and a second MTJ structure. The first MTJ is coupled between a first terminal (FT) and a third terminal. A portion of the first MTJ is configured to include a first barrier layer disposed between a first fixed layer and a free layer (FL). A magnetization direction of the FL is used to store data, the magnetization direction being controlled by an electric field. The second MTJ is coupled between the FT and a second terminal, where a portion of the second MTJ is configured to include a second barrier layer disposed between a second fixed layer and the FL, where a tunnel magnetoresistance of the second barrier layer is used to read the data.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Inventors: Hao MENG, Yong Wee Francis POH, Tze Ho Simon CHAN
  • Patent number: 9218875
    Abstract: A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the secondary selector selects a bit within the multi-bit cell. A plurality of storage units can be commonly coupled to a primary selector, facilitating high density applications.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 22, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yang Hong, Yong Wee Francis Poh, Tze Ho Simon Chan
  • Patent number: 9196356
    Abstract: A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 24, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yang Hong, Yong Wee Francis Poh, Tze Ho Simon Chan
  • Publication number: 20150214238
    Abstract: Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate prepared with an isolation well, a HV well region and first and second wells disposed in the substrate. The memory cell further includes a first transistor having a select gate and a second transistor having a floating gate adjacent to one another and disposed over the second well. The transistors include first and second diffusion regions disposed adjacent to the sides of the gates. A control gate is disposed over the first well and coupled to the floating gate. The control and floating gates include the same gate layer extending across the first and second wells. The control gate includes a capacitor.
    Type: Application
    Filed: April 10, 2015
    Publication date: July 30, 2015
    Inventors: Danny Pak-Chum SHUM, Yong Wee Francis POH, Upinder SINGH, Yuan SUN, Myo Aung MAUNG MAUNG
  • Patent number: 9082964
    Abstract: An embodiment, relates to a phase changeable memory cell. The phase changeable memory cell is formed with an ultra small contact area formed by filament conductive path. This contact area between a heating electrode and phase changeable material layer is determined by the forming of filament path, which is conductive and much smaller in cross-sectional area than the minimum area that can be achieved by lithography. This leads to high heating efficiency and ultra-low programming current. As the disclosed structure has no requirement on endurance for the formed filament and use phase changeable material rather than filament-forming material to provide high on/off resistance ratio, drawbacks of filament-forming material on low endurance and low sensing margin are avoided in the proposed cell structure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 14, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yang Hong, Yong Wee Francis Poh, Tze Ho Simon Chan
  • Patent number: 9076962
    Abstract: A phase changeable memory cell is disclosed. In an embodiment of the invention, a phase changeable memory cell is formed with an ultra-small contact area to reduce the programming current. This contact area between heater electrode and phase changeable material is limited by the thickness of thin films rather than lithographic critical dimension in one dimension. As a result, the contact area is much less than the square of lithographic critical dimension for almost every technology node, which is helps in reducing current. To further reduce the current and improve the heating efficiency, heater electrode is horizontally put with its length being tunable so as to minimize the heat loss flowing through the heater to the terminal that connects to the front end switch device. In addition, above and below the heater layer, low-thermal-conductivity material (LTCM) is used to minimize heat dissipation. This results in reduced power consumption of the phase changeable memory cell with improved reliability.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: July 7, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yang Hong, Yong Wee Francis Poh, Tze Ho Simon Chan
  • Publication number: 20140264243
    Abstract: An embodiment, relates to a phase changeable memory cell. The phase changeable memory cell is formed with an ultra small contact area formed by filament conductive path. This contact area between a heating electrode and phase changeable material layer is determined by the forming of filament path, which is conductive and much smaller in cross-sectional area than the minimum area that can be achieved by lithography. This leads to high heating efficiency and ultra-low programming current. As the disclosed structure has no requirement on endurance for the formed filament and use phase changeable material rather than filament-forming material to provide high on/off resistance ratio, drawbacks of filament-forming material on low endurance and low sensing margin are avoided in the proposed cell structure.
    Type: Application
    Filed: December 27, 2013
    Publication date: September 18, 2014
    Applicant: GLOBAL FOUNDERS Singapore Pte. Ltd.
    Inventors: Yang HONG, Yong Wee, Francis POH, Tze Ho, Simon CHAN
  • Publication number: 20140268990
    Abstract: A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yang HONG, Yong Wee Francis POH, Tze Ho Simon CHAN
  • Publication number: 20140268989
    Abstract: A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the secondary selector selects a bit within the multi-bit cell. A plurality of storage units can be commonly coupled to a primary selector, facilitating high density applications.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yang HONG, Yong Wee, Francis POH, Tze Ho, Simon CHAN
  • Publication number: 20140264244
    Abstract: A phase changeable memory cell is disclosed. In an embodiment of the invention, a phase changeable memory cell is formed with an ultra-small contact area to reduce the programming current. This contact area between heater electrode and phase changeable material is limited by the thickness of thin films rather than lithographic critical dimension in one dimension. As a result, the contact area is much less than the square of lithographic critical dimension for almost every technology node, which is helps in reducing current. To further reduce the current and improve the heating efficiency, heater electrode is horizontally put with its length being tunable so as to minimize the heat loss flowing through the heater to the terminal that connects to the front end switch device. In addition, above and below the heater layer, low-thermal-conductivity material (LTCM) is used to minimize heat dissipation. This results in reduced power consumption of the phase changeable memory cell with improved reliability.
    Type: Application
    Filed: January 23, 2014
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yang HONG, Yong Wee, Francis POH, Tze Ho, Simon CHAN