Patents by Inventor Yongwoo JEONG
Yongwoo JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085940Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Kwanwoo NOH, Sungho SEO, Yongwoo JEONG, Dongwoo NAM, Myungsub SHIN, Hyunkyu JANG
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Publication number: 20240072208Abstract: A display apparatus includes a display panel having a base member, a plate member, and a display part disposed between the base member and the plate member, a vibration layer disposed at a rear surface of the plate member, and an electrode layer disposed at the vibration layer. Further, a signal cable can be provided, which is electrically coupled to the plate member and the electrode layer.Type: ApplicationFiled: August 10, 2023Publication date: February 29, 2024Applicant: LG Display Co., Ltd.Inventors: Uihyeon JEONG, Sooyoun KIM, YongWoo LEE, HwaYoul LEE
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Patent number: 11874695Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.Type: GrantFiled: December 9, 2022Date of Patent: January 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Kwanwoo Noh, Sungho Seo, Yongwoo Jeong, Dongwoo Nam, Myungsub Shin, Hyunkyu Jang
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Publication number: 20230385209Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jeongsu KIM, Kwanwoo NOH, Sungho SEO, Yongwoo JEONG
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Patent number: 11782853Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.Type: GrantFiled: September 7, 2021Date of Patent: October 10, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jeongsu Kim, Kwanwoo Noh, Sungho Seo, Yongwoo Jeong
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Patent number: 11726677Abstract: Disclosed is a storage device which includes an interface circuit that exchanges data with a host device, and a power management unit that supplies a power to the interface circuit. The interface circuit includes a first input terminal receiving a first signal from the host device, a second input terminal receiving a second signal complementary to the first signal from the host device, a receive module processing the first signal and the second signal, a squelch circuit detecting levels of the first signal and the second signal, and a reference clock detector detecting whether a reference clock for operating the storage device is received. The power management unit selectively supplies a power to the squelch circuit based on a result of the detection by the reference clock detector.Type: GrantFiled: January 6, 2021Date of Patent: August 15, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kwanwoo Noh, Sungho Seo, Yongwoo Jeong
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Publication number: 20230112284Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.Type: ApplicationFiled: December 9, 2022Publication date: April 13, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Kwanwoo NOH, Sungho SEO, Yongwoo JEONG, Dongwoo NAM, Myungsub SHIN, Hyunkyu JANG
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Patent number: 11561571Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.Type: GrantFiled: February 19, 2021Date of Patent: January 24, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kwanwoo Noh, Sungho Seo, Yongwoo Jeong, Dongwoo Nam, Myungsub Shin, Hyunkyu Jang
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Publication number: 20220206966Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.Type: ApplicationFiled: September 7, 2021Publication date: June 30, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jeongsu KIM, Kwanwoo NOH, Sungho SEO, Yongwoo JEONG
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Publication number: 20210263550Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.Type: ApplicationFiled: February 19, 2021Publication date: August 26, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kwanwoo NOH, Sungho SEO, Yongwoo JEONG, Dongwoo NAM, Myungsub SHIN, Hyunkyu JANG
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Publication number: 20210216223Abstract: Disclosed is a storage device which includes an interface circuit that exchanges data with a host device, and a power management unit that supplies a power to the interface circuit. The interface circuit includes a first input terminal receiving a first signal from the host device, a second input terminal receiving a second signal complementary to the first signal from the host device, a receive module processing the first signal and the second signal, a squelch circuit detecting levels of the first signal and the second signal, and a reference clock detector detecting whether a reference clock for operating the storage device is received. The power management unit selectively supplies a power to the squelch circuit based on a result of the detection by the reference clock detector.Type: ApplicationFiled: January 6, 2021Publication date: July 15, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kwanwoo NOH, Sungho SEO, Yongwoo JEONG
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Patent number: 10950281Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.Type: GrantFiled: October 17, 2019Date of Patent: March 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yongwoo Jeong, Hwaseok Oh, JinHyeok Choi
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Publication number: 20200051601Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.Type: ApplicationFiled: October 17, 2019Publication date: February 13, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Yongwoo JEONG, Hwaseok OH, JinHyeok CHOI
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Patent number: 10453507Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.Type: GrantFiled: August 24, 2017Date of Patent: October 22, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yongwoo Jeong, Hwaseok Oh, JinHyeok Choi
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Publication number: 20180090191Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.Type: ApplicationFiled: August 24, 2017Publication date: March 29, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Yongwoo JEONG, Hwaseok OH, JinHyeok CHOI