Patents by Inventor Yong Yu

Yong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261311
    Abstract: A display panel and a display apparatus are provided. The display panel includes a display substrate, a first printed circuit board and a second printed circuit board, wherein the display substrate includes a display area and a bonding area located on a side of the display area, the bonding area is connected with the first printed circuit board, and the first printed circuit board is connected with the second printed circuit board through a second flexible printed circuit; and the first printed circuit board is a wiring circuit board mounted with a signal connection line, the second printed circuit board is a drive circuit board mounted with a drive chip, and an orthographic projection of the second printed circuit board on a plane of the display panel does not overlap with an orthographic projection of the display substrate on the plane of the display panel.
    Type: Application
    Filed: April 29, 2025
    Publication date: August 14, 2025
    Inventors: Jiaqin ZHANG, Chang ZHANG, Chuanyan LAN, Qun JIA, Yong YU, Yongle WANG
  • Patent number: 12382718
    Abstract: A semiconductor device may include an active pattern on a substrate, a lower channel pattern on the active pattern and including first and second lower semiconductor patterns, an upper channel pattern on the lower channel pattern and including first and second upper semiconductor patterns, a pair of lower source/drain patterns on opposite sides of the lower channel pattern and a pair of upper source/drain patterns on opposite sides of the upper channel pattern, and a gate electrode surrounding the lower and upper channel patterns. The gate electrode may include a first upper portion between the first and second upper semiconductor patterns, and a first lower portion between the first and second lower semiconductor patterns. Each semiconductor pattern may include a first recess part having a first recess region on a top surface thereof, and a first protrusion part protruding from a bottom surface of the first recess part.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: August 5, 2025
    Assignees: Samsung Electronics Co., Ltd., KOREA UNIVERSITY Research and Business Foundation
    Inventors: Hyun-Yong Yu, Seung Geun Jung
  • Patent number: 12380919
    Abstract: A tunneling device includes a first semiconductor portion disposed on a first oxide substrate, a second semiconductor portion disposed on the first semiconductor portion, and an intermediate layer disposed between the first semiconductor portion and second semiconductor portion. The intermediate layer is a natural oxide film obtained by naturally oxidizing one surface of the second semiconductor portion for a predetermined time.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: August 5, 2025
    Assignee: Korea University Research and Business Foundation
    Inventors: Hyun Yong Yu, Kyu Hyun Han
  • Patent number: 12382625
    Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, and bit lines, word lines, active pillars, and a memory structure that are located on the base. The bit line extends along a first direction, the word line extends along a second direction, the first direction is one of a direction perpendicular to a surface of the base or a direction parallel to the surface of the base, and the second direction is the other of the direction perpendicular to the surface of the base or the direction parallel to the surface of the base. The active pillars are parallel to the base and arranged at intervals, the word line surrounds a channel region of the active pillar, the memory structure surrounds a support region of the active pillar.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: August 5, 2025
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Guangsu Shao, Deyuan Xiao, Yong Yu
  • Patent number: 12376281
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars on the substrate, where each of the active pillars includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: July 29, 2025
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Deyuan Xiao, Yong Yu, Guangsu Shao
  • Publication number: 20250241031
    Abstract: An oxide semiconductor transistor, a method for manufacturing the same, and a semiconductor device including the oxide semiconductor transistor are disclosed. The disclosed oxide semiconductor transistor may include a gate electrode, a p-type oxide semiconductor channel layer disposed opposite the gate electrode, a gate insulating layer between the gate electrode and the oxide semiconductor channel layer, a source electrode and a drain electrode electrically connected to a first region and a second region of the oxide semiconductor channel layer, respectively, and an intermediate layer disposed between the oxide semiconductor channel layer and the source electrode, as well as between the oxide semiconductor channel layer and the drain electrode, the intermediate layer having an oxygen areal density (OAD) higher than an OAD of the oxide semiconductor channel layer.
    Type: Application
    Filed: January 16, 2025
    Publication date: July 24, 2025
    Inventors: Hyun-yong YU, Jongyoun PARK, Sungjoo SONG, Jong-hyun KIM
  • Publication number: 20250240434
    Abstract: A method and apparatus for encrypting an ROI in a HEVC/H.265 video based on a coding unit are disclosed. The method, which is performed by an encryption apparatus, may include identifying a coding unit related to an ROI that is generated for each frame as the frames that constitute a video are partitioned as a tile, and performing selective encryption on the identified coding unit.
    Type: Application
    Filed: August 18, 2023
    Publication date: July 24, 2025
    Inventors: Young-Gab KIM, Jin-Yong YU
  • Publication number: 20250228479
    Abstract: An epidermal biosensor comprising a diffusion layer operable to dissolve a solid-phase epidermal analyte, an enzymatic bioreceptor operable to oxidise the dissolved epidermal analyte from the diffusion layer, a transducer having an interface with the diffusion layer, a processor configured to process electrochemical data from the transducer, and a substrate to which the enzymatic bioreceptor and the transducer are attached. The solid-phase epidermal analyte may include water-insoluble cholesterol and water-soluble lactate. The diffusion-solvation layer may comprise agarose hydrogel and additives including glycerol and/or gelatin to improve mechanical robustness and reduce water evaporation rate of the hydrogel, and ethanol and/or Triton X-100 to facilitate solvation and transportation of hydrophobic analytes.
    Type: Application
    Filed: March 2, 2023
    Publication date: July 17, 2025
    Inventors: Yuxin LIU, Wei Peng GOH, Xinting ZHENG, Yong YU, Chong Li Sherwin TAN, Changyun JIANG, Ruth Theresia ARWANI, Le YANG
  • Patent number: 12363889
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming an silicon pillar on the substrate; pre-processing the silicon pillar, to form an active pillar including a first segment, a second segment, and a third segment, where the second segment includes a first sub-segment and a second sub-segment, and a cross-sectional area of the second sub-segment is smaller than that of the first sub-segment; forming a gate oxide layer; and forming a word line structure surrounding the second segment, where the word line structure includes a first word line structure and a second word line structure that are made of different materials.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: July 15, 2025
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Deyuan Xiao, Yong Yu, Guangsu Shao
  • Patent number: 12356549
    Abstract: A display panel and a display apparatus. The display panel includes a display substrate, a first printed circuit board and a second printed circuit board, wherein the display substrate includes a display area and a bonding area located on a side of the display area, the bonding area is connected with the first printed circuit board through a first flexible printed circuit, and the first printed circuit board is connected with the second printed circuit board through a second flexible printed circuit; and the first printed circuit board is a wiring circuit board mounted with a signal connection line, the second printed circuit board is a drive circuit board mounted with a drive chip, and an orthographic projection of the second printed circuit board on a plane of the display panel does not overlap with an orthographic projection of the display substrate on the plane of the display panel.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: July 8, 2025
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Jiaqin Zhang, Chang Zhang, Chuanyan Lan, Qun Jia, Yong Yu, Yongle Wang
  • Publication number: 20250213621
    Abstract: Cardiopulmonary progenitor exosomes and a preparation method thereof are provided. A culture medium of the cardiopulmonary progenitors is prepared by adopting a preparation method developed by an inventor aiming at the cardiopulmonary progenitors, the supernatant is taken, and the cardiopulmonary progenitor exosomes are isolated and extracted by ultracentrifugation. The applications of the cardiopulmonary progenitor exosomes in reducing the area of cardiac necrosis and fibrosis, promoting the improvement of cardiac function, the proliferation of cardiomyocytes and the angiogenesis of injured hearts are provided, which indicates that they have great potential in preventing and treating cardiovascular diseases.
    Type: Application
    Filed: June 6, 2024
    Publication date: July 3, 2025
    Inventors: Xi-Yong Yu, Yingying Xiao, Luoxing Xia, Jianfeng Qin, Li Wei
  • Publication number: 20250215266
    Abstract: The presently claimed invention relates to dielectric polishing composition and methods thereof. The presently claimed invention particularly relates to a composition comprising: (A) surface-modified colloidal silica particles comprising a negatively-charged group on the surface of the particles, wherein the surface-modified colloidal silica particles have a negative charge, a particle size of from 60 nm to 200 nm, and a zeta potential <?35 mV at a pH in the range of from ?2.0 to ?4.5; (B) first corrosion inhibitor selected from at least one guanidine derivative; (C) second corrosion inhibitor selected from polyacrylamides or polyacrylamide copolymers; (D) at least one iron (III) oxidizer; (E) at least one silicon oxide removal rate enhancer selected from phosphoric acid and salts thereof; (F) at least one stabilizer; and (G) an aqueous medium, wherein the pH of the composition is in the range of from ?2.0 to ?4.5.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 3, 2025
    Inventors: Ching Hsun CHAO, Yong Yu CHEN, Tsung Yu TSAI, Michael LAUTER, Te Yu WEI
  • Patent number: 12349333
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming active pillars arranged at intervals on the substrate, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially along a first direction; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a word line structure on a sidewall of the gate oxide layer, the word line structure includes a first word line structure and a second word line structure that are made of different materials, and the first word line structure is connected to the sidewall of the gate oxide layer, and partially covers the second word line structure.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: July 1, 2025
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Deyuan Xiao, Yong Yu, Guangsu Shao
  • Patent number: 12349332
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: July 1, 2025
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Deyuan Xiao, Yong Yu, Guangsu Shao
  • Publication number: 20250209698
    Abstract: Embodiments of the present application disclose a method, apparatus, device and storage medium of video editing. The method comprises: determining a single-frame processing policy and a video post-processing policy corresponding to a video editing option selected by a user; performing a single-frame processing on video frames of a target video input by the user based on the single-frame processing policy, and caching a single-frame processing result to a single-frame processing list; and forming a video editing sequence of the target video based on the video post-processing policy in combination with the single-frame processing list, and storing the video editing sequence.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 26, 2025
    Inventors: Jingjing Zhuge, Yong Yu, Qiang Zhou, Lexin Tang
  • Patent number: 12336958
    Abstract: The negative pressure generator includes a chamber body with a suction nozzle; a piston, arranged inside the chamber body; and a driving device configured to drive the piston to reciprocated move inside the chamber body so as to generate negative pressure at the suction nozzle.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: June 24, 2025
    Assignee: SHENZHEN SVAKOM TECHNOLOGY CO., LTD
    Inventors: Minchao He, Yong Yu, Guohui Zhang
  • Patent number: 12340742
    Abstract: A display driving circuit, a method for driving a display panel, and a display device are provided, relating to display technologies. The display driving circuit includes a first display driving circuit, a second display driving circuit, a power circuit and a TCON circuit. The first display driving circuit is configured to send a first control signal to the second display driving circuit in response to that a level of the first power signal sent by the power circuit reaches a second level, and send a second control signal to the second display driving circuit in response to that a level of the communication indication signal sent by the TCON circuit reaches a fourth level; the second display driving circuit is configured to: turn off the plurality of pixels in response to the first control signal, and drive the plurality of pixels in response to the second control signal in the state of completing initialization.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: June 24, 2025
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Yong Yu, Hao Sun
  • Patent number: 12317472
    Abstract: A method for manufacturing a semiconductor device includes the following operations. A substrate is provided. Bit lines extending in a first direction are formed on the substrate. A first dielectric layer is formed on the bit lines. The first dielectric layer is etched from top to bottom to form channel holes in the first dielectric layer, in which the channel holes expose the bit lines. A channel layer is formed in each channel hole, in which the channel layer includes a first source/drain area, a channel area and a second source/drain area which are arranged from bottom to top, the first source/drain area is electrically connected to a respective one bit line. Word lines extending in a second direction are formed in the first dielectric layer.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 27, 2025
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Deyuan Xiao, Yong Yu, Guangsu Shao
  • Publication number: 20250160002
    Abstract: Disclosed are low-plasma treatment-based metal transfer technology, high-quality source-drain formation technology, and a method of manufacturing a semiconductor device using the same. The method of manufacturing the semiconductor device includes preparing an oxide substrate, sequentially depositing a contact metal, Ti, and Au on the oxide substrate, performing plasma treatment on the oxide substrate on which the contact metal, the Ti, and the Au are deposited, attaching an organic film on the oxide substrate on which the contact metal, the Ti, and the Au are deposited, and removing oxide of the oxide substrate.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 15, 2025
    Inventors: Hyun-Yong YU, Kyu Hyun HAN
  • Publication number: 20250160001
    Abstract: Disclosed are low-temperature etching-based metal transfer technology, high-quality source-drain formation technology, and a method of manufacturing a semiconductor device using the same. The method of manufacturing the semiconductor device includes preparing an oxide substrate, sequentially depositing a contact metal, Ti, and Au on the oxide substrate, attaching an organic film on the oxide substrate on which the contact metal, Ti, and Au are deposited, and removing oxide of the oxide substrate.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 15, 2025
    Inventors: Hyun-Yong YU, Kyu Hyun HAN