Abstract: This disclosure provides an inter-cell interference coordination method, apparatus, device, and storage medium, the method comprises: predicting a target service load of a target cell in the next period, obtaining a prediction strategy of neighboring cells for a high-coherence neighboring cell in the next period, and determining a cluster state of the target cell based on the prediction strategy of targets and the prediction strategy of neighboring cells; obtaining a prediction strategy of clusters for the cluster where the target cell is located in the next period, and determining that the strategy to be performed by the target cell in the next period is the prediction strategy of targets or the prediction strategy of clusters based on the cluster state.

Abstract: Embodiments of the present application relate to the technical field of communication, and in particular to an interference coordination method of a cell, an interference coordination device of a cell, a server and a storage medium. The interference coordination method of the cell includes: obtaining a strategy information table of a target cell in a next cycle, and the strategy information table includes a first cycle optimizing strategy of the target cell and a second cycle optimizing strategy of each coherent cell of the target cell; obtaining a cluster state of the target cell according to the first cycle optimizing strategy and each second cycle optimizing strategy; and determining an interference coordination strategy of the target cell in the next cycle according to the first cycle optimizing strategy and the cluster state.

Abstract: A spectrum sharing method and apparatus, and a computer storage medium are disclosed. The spectrum sharing method may include: performing load prediction for a first cell to obtain first load prediction data; performing load prediction for a second cell to obtain second load prediction data; and migrating a User Equipment (UE) of the first cell to the second cell and allocating a shared spectrum resource corresponding to the first cell to a third cell, in response to determining according to the first load prediction data and the second load prediction data that the first cell satisfies a migration condition, a standard level of the first cell is higher than or equal to a standard level of the second cell, and a standard level of the third cell is higher than the standard level of the first cell.

Abstract: The present disclosure provides a method for determining a coverage layer cell, including: sending a cell measurement instruction to terminals connected to a target cell; receiving measurement reports reported by the terminals, and determining a neighboring cell set at least partially overlapping a coverage layer of the target cell according to all the reported measurement reports; determining hit cells in the neighboring cell set according to preset cell types and all the measurement reports; and sending a first coverage layer acknowledge request to all the hit cells, and determining, in response to a first coverage layer acknowledge response fed back by any one hit cell of all the hit cells, the hit cell as the coverage layer cell. The present disclosure further provides an electronic device and a computer-readable medium.

Abstract: The present disclosure discloses a lamp body and a lamp cup. An installation ring platform is provided on a bottom of the lamp cup, and the installation ring platform is provided with a plurality of wire clamping grooves the plurality of wire clamping grooves are arranged along a circumferential direction of the installation ring platform; and a bayonet that is provided on a top of the wire clamping groove, and the bayonet is located on a top surface of the installation ring platform.

Abstract: A lamp connector includes an insulating connector body, a first pressing cover, and a second pressing cover. The insulating connector body includes a first electrical connection part, a second electrical connection part, and an electrical connection structure; the first electrical connection part includes a first base, and a first end of the first pressing cover is mounted on the first base through a first rotating shaft structure, a second end of the first pressing cover is fixed to the first base through a first fixing structure. The second electrical connection part includes a second base, and a third end of the second pressing cover is mounted on the second base through a second rotating shaft structure, a fourth end of the second pressing cover is fixed to the second base through a second fixing structure.

Abstract: Provided are a parameter adjustment method, a server, and a storage medium. The parameter adjustment method comprises: acquiring an index value of a first performance index of a device; searching for superiority of each of a plurality of candidate values for a target operation parameter of the device on the basis of the index value of the first performance index, wherein the superiority of each of the plurality of candidate values refers to a superiority level of each of the plurality of candidate values that each of the plurality of candidate values is set to the target operation parameter on the basis of the index value of the first performance index; and selecting one candidate value as a set value of the target operation parameter after the adjustment according to the searched superiority of each of the plurality of candidate values.

Abstract: The present disclosure discloses a lamp body and a lamp cup. An installation ring platform is provided on a bottom of the lamp cup, and the installation ring platform is provided with a plurality of wire clamping grooves the plurality of wire clamping grooves are arranged along a circumferential direction of the installation ring platform; and a bayonet that is provided on a top of the wire clamping groove, and the bayonet is located on a top surface of the installation ring platform.

Abstract: The disclosure discloses a light source module of a luminaire including a light source board, a heat dissipating component, a first sleeving component, and a second sleeving component, wherein the heat dissipating component includes a mounting base portion; the second sleeving component is sleeved on the first sleeving component and presses the light source board on the mounting base portion; the light source board includes illuminators; the first sleeving component has an avoidance space, and the illuminators are located in the avoidance space; and at least a region, opposing to the illuminators, of the second sleeving component is a light transmission region.

Abstract: A lamp connector includes an insulating connector body, a first pressing cover, and a second pressing cover. The insulating connector body includes a first electrical connection part, a second electrical connection part, and an electrical connection structure; the first electrical connection part includes a first base, and a first end of the first pressing cover is mounted on the first base through a first rotating shaft structure, a second end of the first pressing cover is fixed to the first base through a first fixing structure. The second electrical connection part includes a second base, and a third end of the second pressing cover is mounted on the second base through a second rotating shaft structure, a fourth end of the second pressing cover is fixed to the second base through a second fixing structure.

Abstract: The disclosure discloses a light source module of a luminaire including a light source board, a heat dissipating component, a first sleeving component, and a second sleeving component, wherein the heat dissipating component includes a mounting base portion; the second sleeving component is sleeved on the first sleeving component and presses the light source board on the mounting base portion; the light source board includes illuminators; the first sleeving component has an avoidance space, and the illuminators are located in the avoidance space; and at least a region, opposing to the illuminators, of the second sleeving component is a light transmission region.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distribution show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.