Abstract: A packet processing method includes, when data at a first location in a packet arrives at a channel forwarding layer, determining a first multiframe used to bear the data at the first location, and determining a real timestamp of the first multiframe based on a timestamp of a second multiframe in a channel in which the first multiframe is located. The second multiframe is an Xth multiframe previous to the first multiframe in the channel, X?0, and the timestamp of the second multiframe is a timestamp at which a second location of the second multiframe arrives at a physical layer such that packet stamping is implemented in the Ethernet leased line technology.

Abstract: This application provides an in-vehicle communication method, an apparatus, and a system. The system including: multiple gateways connected through a bus, where an ASN apparatus is disposed in each gateway. The ASN apparatus sends, to one or more of an in-vehicle service node, a controller, data carried in an ATU that is decapsulated by the ASN apparatus, or sends, to another gateway connected to the gateway, an ATU encapsulated by the ASN apparatus; and the ATU is obtained by encapsulating data of each in-vehicle service based on a physical layer coding rule that adapts to the bus; and the in-vehicle service node, the controller, or the in-vehicle networked terminal connected to the gateway, configured to receive decapsulated data sent by the gateway or send, to the gateway, data corresponding to an in-vehicle service of the in-vehicle service node, the controller, or the in-vehicle networked terminal.

Abstract: A sending method, a receiving method, an apparatus, a system, a device, and a storage medium. The receiving method includes: obtaining an encoded data block, where the encoded data block includes a plurality of data blocks, a plurality of first parity bits, and an FEC parity bit, the plurality of first parity bits are in one-to-one correspondence with the plurality of data blocks, and the FEC parity bit corresponds to the plurality of data blocks; and then checking the corresponding data blocks based on the plurality of first parity bits and/or the FEC parity bit, to obtain a decoding result of the encoded data block.

Abstract: Embodiments of this application disclose a synchronization method and a device. A device marks, based on a preset period, a periodic code block in a data bitstream to be sent from a MAC layer to a PHY layer. The device sends the data bitstream to a peer device through the PHY layer, records a sending time of each periodic code block as a first timestamp during sending, and returns the first timestamp to the MAC layer. By marking a timestamp for the periodic code block received from the MAC layer, the device sets a PHY-layer-based time reference scale (namely, the first timestamp) at the PHY layer.

Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position heads proximate to a recording medium of the disks; a spindle motor configured for rotating the one or more disks; and one or more processing devices comprising a servo control processor. The servo control processor is configured to receive a spindle speed error signal indicative of an error in a rotational speed of the spindle motor. The servo control processor is further configured to output an initial frequency offset signal, wherein the initial frequency offset signal is proportional to the spindle speed error signal.

Abstract: According to embodiments of the present disclosure, a method and a chip for cyclic code encoding, a circuit component, and an electronic device are provided. The method includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence; generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols; generating the (N?K) parity symbols based on the first parity sequence and the second parity sequence.

Abstract: A method for determining a transmission slot includes determining, by a target device, a sending slot based on a receiving slot and a latency correction parameter, or determining, by the target device, a receiving slot based on a sending slot and a latency correction parameter.

Abstract: A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.

Abstract: Embodiments of this application disclose a synchronization method and a device. First, a device marks, based on a preset period, a periodic code block in a data bitstream to be sent from a MAC layer to a PHY layer, then sends the data bitstream to a peer device through the PHY layer, records a sending time of each periodic code block as a first timestamp during sending, and returns the first timestamp to the MAC layer. To be specific, by marking a timestamp for the periodic code block received from the MAC layer, the device sets a PHY-layer-based time reference scale (namely, the first timestamp) at the PHY layer.

Abstract: A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.

Abstract: A flexible Ethernet (FlexE) frame forwarding method, including receiving a first frame through a FlexE client input channel, obtaining a first channel identifier used to indicate the FlexE client input channel and a first subchannel identifier carried in the first frame, where the first subchannel identifier is used to indicate a logical subchannel of the FlexE client input channel, searching a preset forwarding table based on the first channel identifier and the first subchannel identifier to obtain a second channel identifier and a second subchannel identifier, where the second channel identifier is used to indicate a FlexE client output channel, and the second subchannel identifier is used to indicate a logical subchannel of the FlexE client output channel, and forwarding the first frame based on the second channel identifier and the second subchannel identifier.

Abstract: The invention disclose a flexible Ethernet frame forwarding method, including: receiving a first frame through a FlexE client input channel; obtaining a first channel identifier used to indicate the FlexE client input channel and a first subchannel identifier carried in the first frame, where the first subchannel identifier is used to indicate a logical subchannel of the FlexE client input channel; searching a preset forwarding table based on the first channel identifier and the first subchannel identifier to obtain a second channel identifier and a second subchannel identifier, where the second channel identifier is used to indicate a FlexE client output channel, and the second subchannel identifier is used to indicate a logical subchannel of the FlexE client output channel; and forwarding the first frame based on the second channel identifier and the second subchannel identifier.

Abstract: A programmable logic processor (PLC) with multiple PLC functions is disclosed. The PLC includes at least one memory storing at least one of a plurality of programs or data, and one or more processor assigned to each of the PLC function and couple to the memory. The PLC functions are run in parallel. A method of operating the PLC and a PLC system with multiple processors are also disclosed.

Abstract: A programmable logic processor (PLC) with multiple PLC functions is disclosed. The PLC includes at least one memory storing at least one of a plurality of programs or data, and one or more processor assigned to each of the PLC function and couple to the memory. The PLC functions are run in parallel. A method of operating the PLC and a PLC system with multiple processors are also disclosed.