Abstract: Embodiments of this application provide a human-computer interaction method, a human-computer interaction apparatus, and a storage medium. The method includes: displaying a human-computer interface, where the human-computer interface includes an operable object and a visual stimulus region; and executing a first operational command on the operable object, where the first operational command is determined based on a first signal, the first signal is an electroencephalography signal generated when a user gazes at a first region, the first region is one of a plurality of regions around the visual stimulus region, different electroencephalography signals are generated when the user gazes at different regions of the plurality of regions, and the different electroencephalography signals indicate to execute different operational commands related to the operable object.

Abstract: Branch prediction techniques are described that can improve the performance of pipelined microprocessors. A microprocessor with a hierarchical branch prediction structure is presented. The hierarchy of branch predictors includes: a multi-cycle predictor that provides very accurate branch predictions, but with a latency of multiple cycles; a small and simple branch predictor that can provide branch predictions for a sub-set of instructions with zero-cycle latency; and a fast, intermediate level branch predictor that provides relatively accurate branch prediction, while still having a low, but non-zero instruction prediction latency of only one cycle, for example. To improve operation, the higher accuracy, higher latency branch direction predictor and the fast, lower latency branch direction predictor can share a common target predictor.

Abstract: Branch prediction techniques are described that can improve the performance of pipelined microprocessors. A microprocessor with a hierarchical branch prediction structure is presented. The hierarchy of branch predictors includes: a multi-cycle predictor that provides very accurate branch predictions, but with a latency of multiple cycles; a small and simple branch predictor that can provide branch predictions for a sub-set of instructions with zero-cycle latency; and a fast, intermediate level branch predictor that provides relatively accurate branch prediction, while still having a low, but non-zero instruction prediction latency of only one cycle, for example. To improve operation, the higher accuracy, higher latency branch direction predictor and the fast, lower latency branch direction predictor can share a common target predictor.