Abstract: A non-volatile memory circuit for use with an E.sup.2 PROM includes redundant, parallel connected, floating node MOSFET memory cells for storing complementary information. The non-volatile memory cells are connected in parallel to a volatile memory circuit via a voltage level shifter circuit for writing operations, and via twin mixed PMOS and NMOS transistors for reading operations. With the combined complementary non-volatile memory cells and the twin mixed pairs of transistors, the stored information is retained in the event that one of the memory cells fails.

Abstract: An MOS transistor device is formed in a semiconductor substrate of one type and has a source and drain of the opposite type. The transistor channel area between the source and drain is divided into three areas: a portion which abuts the source, a portion which abuts the drain and a portion which is between the other two channel portions. The transistor has three gates, including two gates and which are formed in a first layer of polysilicon and a third gate which is formed in a second layer of polysilicon. The first gate is positioned over the first portion of the transistor channel area abutting the source. The second gate overlies the second portion of the transistor channel area abutting the drain. The third gate 126 is positioned between the other two gates, overlies the third portion of the transistor channel area, and partially overlaps the first and second gates. The third gate is connected to the first so that the first and third gates together form a single gate of an MOS transistor device.