Patents by Inventor Yongchao Bian

Yongchao Bian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240193557
    Abstract: The disclosure relates to the technical field of computers. Disclosed are a digital currency management method, apparatus and system. A specific implementation of the method includes: sending one or more first digital currencies to a first currency management apparatus corresponding to a first client, where the one or more first digital currencies belong to one or more second currency management apparatuses different from the first currency management apparatus; and receiving a second digital currency, which is generated by the first currency management apparatus according to the one or more first digital currencies, where the denomination of the second digital currency is equal to the sum of denominations of the one or more first digital currencies.
    Type: Application
    Filed: April 15, 2022
    Publication date: June 13, 2024
    Inventors: Changchun MU, Gang DI, Xinyu ZHAO, Peidong CUI, Ting WANG, Yongchao BIAN
  • Publication number: 20240193594
    Abstract: The present disclosure relates to a method, terminal and system for splitting, and managing a digital currency in a transaction. The method includes: determining a first transaction request indicating a digital currency and first transaction information; generating second transaction information including a second transaction amount according to the first transaction information; respectively signing the first transaction information and the second transaction information by using a private key of a first terminal; generating a first trust chain according to the signed first transaction information and the digital currency, and generating a second trust chain according to the signed second transaction information and the digital currency; and sending the first trust chain to a second terminal, so that the second terminal and the first terminal achieve, according to the first trust chain, an offline transaction corresponding to the first transaction amount included in the first transaction information.
    Type: Application
    Filed: April 15, 2022
    Publication date: June 13, 2024
    Inventors: Changchun MU, Gang DI, Xinyu ZHAO, Peidong CUI, Jingdan ZOU, Hongxue ZHANG, Yongchao BIAN
  • Publication number: 20240177151
    Abstract: Methods and apparatuses for generating, verifying and storing a transaction voucher, devices and a system are provided. The method includes: in response to a received transaction request, chain structure data of a digital currency is acquired, the chain structure data including a first currency string (S101); and a transaction voucher corresponding to a denomination of a current transaction is generated based on the chain structure data, the transaction voucher including a second currency string of a corresponding denomination and a second sub-chain, and the second sub-chain including current transaction information of the second currency string (S102). On the one hand, a pay warrant is provided for a transaction, so that the transaction is traceable, and the security of the transaction is ensured. On the other hand, the reading and storage efficiency of transaction data can be improved, and the transaction efficiency and the user experience can also be improved.
    Type: Application
    Filed: March 21, 2022
    Publication date: May 30, 2024
    Inventors: Wei LIANG, Kefeng XU, Yongchao BIAN
  • Patent number: 7524235
    Abstract: This invention provides a method for eliminating the surface stress of a silicon wafer comprising forming one or more anti-stress groove(s) on the surface of the silicon wafer. These anti-stress grooves can reduce or eliminate the surface stress of silicon wafer effectively to avoid the formation of slip lines and dislocation arrangements, which may induce the p-n junction to conduct or the leakage current to increase. The process is highly efficient and low in cost. It is simple to manage and does not require additional equipment beyond that already used for processing of silicon wafers.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: April 28, 2009
    Inventors: Yuling Liu, Jianxin Zhang, Weiwei Li, Yanyan Huang, Yongchao Bian, Na Liu
  • Publication number: 20070298690
    Abstract: This invention provides a method for eliminating the surface stress of a silicon wafer comprising forming one or more anti-stress groove(s) on the surface of the silicon wafer. These anti-stress grooves can reduce or eliminate the surface stress of silicon wafer effectively to avoid the formation of slip lines and dislocation arrangements, which may induce the p-n junction to conduct or the leakage current to increase. The process is highly efficient and low in cost. It is simple to manage and does not require additional equipment beyond that already used for processing of silicon wafers.
    Type: Application
    Filed: May 24, 2007
    Publication date: December 27, 2007
    Inventors: Yuling LIU, Jianxin ZHANG, Weiwei LI, Yanyan HUANG, Yongchao BIAN, Na LIU