Patents by Inventor Yongchao Ji

Yongchao Ji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Decoupling capacitive arrangement to manage power integrity
    Patent number: 9844135
    Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: December 12, 2017
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Feng Wu, Yongchao Ji, Yang Tang, Stephen Scearce, Shunjia Liu, Shaochun Tang
  • Decoupling Capacitive Arrangement to Manage Power Integrity
    Publication number: 20160073500
    Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 10, 2016
    Inventors: Feng Wu, Yongchao Ji, Yang Tang, Stephen Scearce, Shunjia Liu, Shaochun Tang