Abstract: A battery pack includes: a battery pack housing; a cell group including multiple cells and accommodated in the battery pack housing; and a monitoring device configured to monitor an ambient temperature at one temperature measurement point or an ambient temperature at each of multiple temperature measurement points in the battery pack housing. A cell includes multiple cell layers, the battery pack further includes a controller configured to control a charging process of the battery pack or a discharging process of the battery pack, the monitoring device is further configured to transmit the monitored ambient temperature to the controller, and the controller is further configured to determine a cell layer temperature of a target cell layer among the multiple cell layers based on at least one ambient temperature and control, based on the cell layer temperature of the target cell layer, the battery pack to be charged or discharge electricity.

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.