Abstract: A circuit for controlling a DC voltage source current includes a low-voltage DC bus capacitor, a first set of power electronics half-bridge units, a first set of branch circuit inductors, and a first set of DC switches. All of the first set of power electronics half-bridge units are connected in parallel between a positive pole and a negative pole of a low-voltage DC bus and are also connected in parallel with the low-voltage DC bus capacitor, an output neutral point of each power electronics half-bridge unit is connected in series with one of the first set of branch circuit inductors and one of the first set of DC switches to form one of a first set of current-sharing branch circuits, and each power electronics half-bridge unit and the corresponding current-sharing branch circuit are used to be connected with a DC voltage source to form a DC voltage source branch circuit.

Abstract: The present disclosure provides a multi-level converter with triangle topology and control method thereof, related to the technical field of multi-level converters. In the converter, n DC capacitors connected in series form a vertical edge of a triangle and are as a DC bus, n switching tubes connected in series form a bevel edge of the triangle, switching tubes each connected between a neutral point of the DC bus corresponding to each layer and a point for connecting the switching tube on the bevel edge form a horizontal edge. Each time the layer is expanded by one, the number of levels increases by one. When a voltage across each capacitor is E, an AC output terminal Xn may output a total of n+1 levels.

Abstract: The present disclosure provides a multi-level converter with triangle topology and control method thereof, related to the technical field of multi-level converters. In the converter, n DC capacitors connected in series form a vertical edge of a triangle and are as a DC bus, n switching tubes connected in series form a bevel edge of the triangle, switching tubes each connected between a neutral point of the DC bus corresponding to each layer and a point for connecting the switching tube on the bevel edge form a horizontal edge. Each time the layer is expanded by one, the number of levels increases by one. When a voltage across each capacitor is E, an AC output terminal Xn may output a total of n+1 levels.

Abstract: The present disclosure provides a single carrier based multilevel modulation method, a single carrier based multilevel modulation device, and a storage medium. In each control period, a modulated wave value corresponding to each of n switch pairs is obtained according to a reference voltage to obtain n modulated wave values, a triangular carrier having an amplitude of n is generated and compared with each of the n modulated wave values to obtain control signals for each of the n switch pairs, and for each phase, the control signals are input to the corresponding switch pairs of the phase bridge.

Abstract: The present disclosure provides a single carrier based multilevel modulation method, a single carrier based multilevel modulation device, and a storage medium. In each control period, a modulated wave value corresponding to each of n switch pairs is obtained according to a reference voltage to obtain n modulated wave values, a triangular carrier having an amplitude of n is generated and compared with each of the n modulated wave values to obtain control signals for each of the n switch pairs, and for each phase, the control signals are input to the corresponding switch pairs of the phase bridge.

Abstract: A method and a device for voltage balancing of DC bus capacitors of an NPC four-level inverter are disclosed. The method includes: determining an optimal zero-sequence voltage, determining an actual reference voltage of each phase based on the optimal zero-sequence voltage; comparing respectively three preset carrier signals with the actual reference voltage of each phase to obtain three first control signals; determining three duty-cycle adjustment values based on a voltage of the intermediate bus capacitor; adjusting correspondingly the three first control signals based the three duty-cycle adjustment values to obtain three second control signals; inputting correspondingly the three second control signals to three first switches of an upper bridge corresponding to each phase; and inputting correspondingly complementary signals of the three second control signals to three second switches of a lower bridge corresponding to each phase.

Abstract: A method and a device for voltage balancing of DC bus capacitors of an NPC four-level inverter are disclosed. The method includes: determining an optimal zero-sequence voltage, determining an actual reference voltage of each phase based on the optimal zero-sequence voltage; comparing respectively three preset carrier signals with the actual reference voltage of each phase to obtain three first control signals; determining three duty-cycle adjustment values based on a voltage of the intermediate bus capacitor; adjusting correspondingly the three first control signals based the three duty-cycle adjustment values to obtain three second control signals; inputting correspondingly the three second control signals to three first switches of an upper bridge corresponding to each phase; and inputting correspondingly complementary signals of the three second control signals to three second switches of a lower bridge corresponding to each phase.