Abstract: Systems, devices, and methods for fabricating slit structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a method includes providing a semiconductor structure including a first region including a first trench structure and a second region including a second trench structure, where the semiconductor structure includes a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure from an opening of the second trench structure to a bottom of the second trench structure along a first direction. At least one part of the second sacrificial film is etched, while at least one part of the first sacrificial film remains to cover the first trench structure.

Abstract: Embodiments of wet processing systems and methods for uniform wet processing are disclosed. A method described in the present disclosure includes measuring one or more wafer characteristics of a wafer using a plurality of detectors and determining a wafer profile of the wafer based on the measured one or more wafer characteristics. The method also includes setting first and second sets of wet processing parameters of a wet processing system for respective first and second wafer regions based on the wafer profile, where a value of at least one wet processing parameter is different between the first and second sets of wet processing parameters. The method further includes performing wet processing on the wafer by dispensing one or more chemicals onto the first and second wafer regions according to the respective first and second sets of wet processing parameters.

Abstract: Examples of the present application disclose a semiconductor device and a fabrication method thereof and a memory system. The semiconductor device includes: a stack structure including first regions and second regions; channel structures that are located in the first regions and penetrate through the stack structure along a first direction; and gate line isolation structures that are located in the second regions and extend along a second direction, wherein the gate line isolation structures penetrate through the stack structure along the first direction and are in a concavo-convex shape along a third direction.

Abstract: Methods for forming a 3D memory device are provided. A method includes the following operations. A stack structure is formed in a staircase region and an array region. A dielectric material layer is formed over the array region and the staircase region. An etch mask layer is coated over the dielectric material layer. The etch mask layer, on a first surface away from the dielectric material layer, is planarized. The dielectric material layer and a remaining portion of the etch mask layer are etched to form a dielectric layer over the staircase region and the array region.

Abstract: The disclosure provides a motor and a motor assembling method. The motor includes a housing having a bottom and a wall portion extending from an edge of the bottom along an axial direction, and a lid connected to the housing on one side in the axial direction of the bottom of the housing. A surface on the one side in the axial direction of the bottom of the housing has a first connection surface. Housing portions on an inside and an outside in a radial direction of the first connection surface are respectively bent in opposite directions intersecting the first connection surface, which ensures sufficient working space when performing work for connecting the housing and the lid.

Abstract: This disclosure provides a motor. The motor includes a housing and a lid molded by pressing. The lid includes a first wall portion extending along an axial direction. One side in the axial direction of the first wall portion is tightly fitted or loose-fitted to the housing, and the other side in the axial direction of the first wall portion is connected to an external device. This structure facilitates coaxial alignment and connection between the housing and the lid and reduces costs.

Abstract: In one aspect, a method for forming a 3D memory device is disclosed. A selective epitaxial sacrificial layer is formed above a substrate, and a dielectric stack is formed above the selective epitaxial sacrificial layer. A first opening extending vertically through the dielectric stack and the selective epitaxial sacrificial layer is formed. A portion of the first opening extending vertically through the selective epitaxial sacrificial layer is enlarged. A memory film and a semiconductor channel are subsequently formed in this order along sidewalls and a bottom surface of the first opening. The selective epitaxial sacrificial layer is removed to form a cavity exposing a portion of the memory film. The portion of the memory film exposed in the cavity is removed to expose a portion of the semiconductor channel. A selective epitaxial layer is epitaxially grown from the substrate to fill the cavity and be in contact with the portion of the semiconductor channel.

Abstract: A memory device fabrication method includes providing a semiconductor structure having a core area and a contact area arranged next to each other along a first direction. The semiconductor structure includes dielectric layer pairs that include first and second dielectric layers stacked in an alternating manner in a second direction approximately perpendicular to the first direction. The method further includes performing etching to form channel holes penetrating the dielectric layer pairs. The channel holes include first channel holes in the contact area and second channel holes in the core area. The first channel holes surround a contact region. The method also includes substituting portions of the second dielectric layers that surround the plurality of first channel holes with a protection material to form a protection wall that surrounds the contact region.

Abstract: A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, a channel hole structure in the conductor/insulator stack, and a gate line slit (GLS) structure. The GLS structure includes a main section and an end section. The main section extends along a first direction and has a first width measured along a second direction that is perpendicular to the first direction. The end section has a second width measured along the second direction. The second width is larger than the first width.

Abstract: A fabrication method of a semiconductor structure includes forming a stack structure and a memory channel structure on a substrate. The memory channel structure penetrates through the stack structure along a stack direction and extends into the substrate to form an extension part. The memory channel structure includes a memory function layer and a channel layer. The method further includes removing the substrate and exposing the extension part, and forming a sacrificial layer on a side of the stack structure where the substrate is removed from. The sacrificial layer wraps a part of the exposed extension part. The method also includes removing the memory function layer in the unwrapped extension part and exposing the corresponding channel layer, removing the sacrificial layer, exposing the remaining memory function layer in the extension part, and forming a semiconductor layer on a side of the stack structure where the sacrificial layer is removed from.

Abstract: A method of manufacturing a semiconductor device includes providing a stack including interlayer sacrifice layers and interlayer insulation layers stacked alternatively. The stack includes a core region and a periphery region distributed along a first direction. The method also includes forming a gate line slit penetrating the stack and extending along the first direction. The gate line slit includes a first slit and a second slit interconnected with each other. The periphery region includes the first slit. The core region includes the second slit. The width of the first slit along the second direction is greater than the width of the second slit along the second direction. The second direction intersects with the first direction. The method further includes forming an isolation section in at least the first slit.

Abstract: The disclosure provides a motor and a motor assembling method. The motor includes a housing having a bottom and a wall portion extending from an edge of the bottom along an axial direction, and a lid connected to the housing on one side in the axial direction of the bottom of the housing. A surface on the one side in the axial direction of the bottom of the housing has a first connection surface. Housing portions on an inside and an outside in a radial direction of the first connection surface are respectively bent in opposite directions intersecting the first connection surface, which ensures sufficient working space when performing work for connecting the housing and the lid.

Abstract: This disclosure provides a motor. The motor includes a housing and a lid molded by pressing. The lid includes a first wall portion extending along an axial direction. One side in the axial direction of the first wall portion is tightly fitted or loose-fitted to the housing, and the other side in the axial direction of the first wall portion is connected to an external device. This structure facilitates coaxial alignment and connection between the housing and the lid and reduces costs.

Abstract: Methods for forming a 3D memory device are provided. A method includes the following operations. A stack structure is formed in a staircase region and an array region. A dielectric material layer is formed over the array region and the staircase region. An etch mask layer is coated over the dielectric material layer. The etch mask layer, on a first surface away from the dielectric material layer, is planarized. The dielectric material layer and a remaining portion of the etch mask layer are etched to form a dielectric layer over the staircase region and the array region.

Abstract: In one aspect, a method for forming a 3D memory device is disclosed. A selective epitaxial sacrificial layer is formed above a substrate, and a dielectric stack is formed above the selective epitaxial sacrificial layer. A first opening extending vertically through the dielectric stack and the selective epitaxial sacrificial layer is formed. A portion of the first opening extending vertically through the selective epitaxial sacrificial layer is enlarged. A memory film and a semiconductor channel are subsequently formed in this order along sidewalls and a bottom surface of the first opening. The selective epitaxial sacrificial layer is removed to form a cavity exposing a portion of the memory film. The portion of the memory film exposed in the cavity is removed to expose a portion of the semiconductor channel. A selective epitaxial layer is epitaxially grown from the substrate to fill the cavity and be in contact with the portion of the semiconductor channel.

Abstract: The present application relates to a landing ramp, which includes a ramp body; the ramp body includes an inclined ramp, a granule retaining dam disposed at the lower end of the inclined ramp and protruding from a slope of the inclined ramp, and a deceleration ramp disposed on one side of the granule retaining dam away from the inclined ramp; a dry snow grass sliding blanket is provided on the deceleration ramp, a dry snow granule layer is provided on the inclined ramp and the dry snow grass sliding blanket; the dry snow grass sliding blanket includes a mounting mesh plate and a dry grass body provided on the mounting mesh plate, there are multiply dry grass body spacingly distributed, a dry snow granule is filled between the dry grass bodies, the aperture of the mounting mesh plate is smaller than the diameter of a dry snow granule.

Abstract: Embodiments of 3D memory devices having a pocket structure in memory strings and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a selective epitaxial layer on the substrate, a memory stack including interleaved conductive layers and dielectric layers on the selective epitaxial layer, and a memory string including a channel structure extending vertically in the memory stack and a pocket structure extending vertically in the selective epitaxial layer. The memory string includes a semiconductor channel extending vertically in the channel structure, and extending vertically and laterally in the pocket structure and in contact with the selective epitaxial layer.

Abstract: Embodiments of wet processing systems and methods for uniform wet processing are disclosed. A method described in the present disclosure includes measuring one or more wafer characteristics of a wafer using a plurality of detectors and determining a wafer profile of the wafer based on the measured one or more wafer characteristics. The method also includes setting first and second sets of wet processing parameters of a wet processing system for respective first and second wafer regions based on the wafer profile, where a value of at least one wet processing parameter is different between the first and second sets of wet processing parameters. The method further includes performing wet processing on the wafer by dispensing one or more chemicals onto the first and second wafer regions according to the respective first and second sets of wet processing parameters.

Abstract: Embodiments of three-dimensional (3D) memory devices with an enlarged joint critical dimension and methods for forming the same are disclosed. In an example, a 3D memory device is disclosed. The 3D memory device includes a substrate, a memory stack having a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the first memory stack and having a memory film along a sidewall of the memory string. The memory film includes a discontinuous blocking layer interposed by the dielectric layers.

Abstract: Aspects of the disclosure provide a semiconductor device and a method for fabricating the same. The method for fabricating the semiconductor device can include forming a stack of alternating first insulating layers and first sacrificial layers over a semiconductor substrate, and forming a staircase in the stack having a plurality of steps, with at least a first step of the staircase including a first sacrificial layer of the first sacrificial layers over a first insulating layer of the first insulating layers. Further, the method can include forming a recess in the first sacrificial layer, forming a second sacrificial layer in the recess, and replacing a portion of the first sacrificial layer and the second sacrificial layer with a conductive material that forms a contact pad.