Patents by Inventor Yonggang Yong LI

Yonggang Yong LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STRESS MITIGATION ARCHITECTURES FOR GLASS CORE SUBSTRATES
    Publication number: 20250112140
    Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Rahul BHURE, Mitchell PAGE, Joseph PEOPLES, Jieying KONG, Nicholas S. HAEHN, Astitva TRIPATHI, Bainye Francoise ANGOUA, Yosef KORNBLUTH, Daniel ROSALES-YEOMANS, Joshua STACEY, Aaditya Anand CANDADAI, Yonggang Yong LI, Tchefor NDUKUM, Scott COATNEY, Gang DUAN, Jesse JONES, Srinivas Venkata Ramanuja PIETAMBARAM, Dilan SENEVIRATNE, Matthew ANDERSON
  • THROUGH GLASS VIA (TGV) WITH MODULATED PROFILE FOR CORE STRESS REDUCTION
    Publication number: 20250113434
    Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. In an embodiment a corner at a junction between the sidewall and the first surface is rounded. In an embodiment, a via is provided in the opening, where the via is electrically conductive.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Bai NIE, Mitchell PAGE, Junxin WANG, Srinivas Venkata Ramanuja PIETAMBARAM, Haifa HARIRI, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Hongxia FENG, Haobo CHEN, Bohan SHAN, Hiroki TANAKA, Leonel R. ARANA, Yonggang Yong LI
  • DEEP CAVITY METALLIZATION AND FIDUCIAL ARRANGEMENTS FOR EMBEDDED DIE AND ASSEMBLY THEREOF ON INTEGRATED CIRCUIT PACKAGING
    Publication number: 20250112162
    Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.
    Type: Application
    Filed: September 30, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Zheng Kang, Tchefor Ndukum, Yosuke Kanaoka, Jeremy Ecton, Gang Duan, Jefferson Kaplan, Yonggang Yong Li, Minglu Liu, Brandon C. Marin, Bai Nie, Srinivas Pietambaram, Shriya Seshadri, Bohan Shan, Deniz Turan, Vishal Bhimrao Zade
  • GLASS CORE PROTECTION USING PERIPHERAL BUFFER LAYERS
    Publication number: 20250112136
    Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
  • Embedded circuit patterning feature selective electroless
    Patent number: 10586715
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Yonggang Yong Li, Aritra Dhar, Dilan Seneviratne, Jon M. Williams
  • EMBEDED CIRCUIT PATTERNING FEATURE SELECTIVE ELECTROLESS COPPER PLATING
    Publication number: 20170243762
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Application
    Filed: May 5, 2017
    Publication date: August 24, 2017
    Inventors: Yonggang Yong LI, Aritra DHAR, Dilan SENEVIRATNE, Jon M. WILLIAMS
  • Embedded circuit patterning feature selective electroless copper plating
    Patent number: 9646854
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Yonggang Yong Li, Aritra Dhar, Dilan Seneviratne, Jon M. Williams
  • MICROELECTRONIC BUILD-UP LAYERS AND METHODS OF FORMING THE SAME
    Publication number: 20160374210
    Abstract: A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess.
    Type: Application
    Filed: February 16, 2015
    Publication date: December 22, 2016
    Applicant: INTEL CORPORATION
    Inventors: Brandon C. MARIN, Trina GHOSH DASTIDAR, Yonggang Yong LI, Dilan SENEVIRATNE
  • EMBEDDED CIRCUIT PATTERNINGG FEATURE SELECTIVE ELECTROLESS COPPER PLATING
    Publication number: 20150279731
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Yonggang Yong LI, Aritra DHAR, Dilan SENEVIRATNE, Jon M. WILLIAMS