Patents by Inventor Yonggang Yong LI

Yonggang Yong LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Embedded circuit patterning feature selective electroless
    Patent number: 10586715
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Yonggang Yong Li, Aritra Dhar, Dilan Seneviratne, Jon M. Williams
  • EMBEDED CIRCUIT PATTERNING FEATURE SELECTIVE ELECTROLESS COPPER PLATING
    Publication number: 20170243762
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Application
    Filed: May 5, 2017
    Publication date: August 24, 2017
    Inventors: Yonggang Yong LI, Aritra DHAR, Dilan SENEVIRATNE, Jon M. WILLIAMS
  • Embedded circuit patterning feature selective electroless copper plating
    Patent number: 9646854
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Yonggang Yong Li, Aritra Dhar, Dilan Seneviratne, Jon M. Williams
  • MICROELECTRONIC BUILD-UP LAYERS AND METHODS OF FORMING THE SAME
    Publication number: 20160374210
    Abstract: A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess.
    Type: Application
    Filed: February 16, 2015
    Publication date: December 22, 2016
    Applicant: INTEL CORPORATION
    Inventors: Brandon C. MARIN, Trina GHOSH DASTIDAR, Yonggang Yong LI, Dilan SENEVIRATNE
  • EMBEDDED CIRCUIT PATTERNINGG FEATURE SELECTIVE ELECTROLESS COPPER PLATING
    Publication number: 20150279731
    Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Yonggang Yong LI, Aritra DHAR, Dilan SENEVIRATNE, Jon M. WILLIAMS