Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches.

Abstract: FinFET semiconductor devices and fabrication methods are provided. Discrete fins are formed on a substrate. An insulation layer is formed on the substrate between the discrete fins, the insulation layer having a top surface lower than a top surface of the fin and covering a portion of a sidewall surface of the fin. A sidewall spacer is formed covering the sidewall surface of the fin and exposing the top surface of the fin. A top portion of the fin is selectively nitrided to convert a thickness portion of the fin into a semiconductor nitride layer on a remainder fin. The semiconductor nitride layer is removed to form an opening on the remainder fin and between adjacent sidewall spacers. A stress layer is formed to fill the opening.

Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into ? form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a ?-shaped recess with a cuspate bottom.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches.

Abstract: FinFET semiconductor devices and fabrication methods are provided. Discrete fins are formed on a substrate. An insulation layer is formed on the substrate between the discrete fins, the insulation layer having a top surface lower than a top surface of the fin and covering a portion of a sidewall surface of the fin. A sidewall spacer is formed covering the sidewall surface of the fin and exposing the top surface of the fin. A top portion of the fin is selectively nitrided to convert a thickness portion of the fin into a semiconductor nitride layer on a remainder fin. The semiconductor nitride layer is removed to form an opening on the remainder fin and between adjacent sidewall spacers. A stress layer is formed to fill the opening.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches.

Abstract: A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches.

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate having a first region; and forming a first gate structure on a surface of the semiconductor substrate in the first region. The method also includes forming trenches in the semiconductor substrate at both sides of the first gate structure; and forming a first stress layer with one surface lower than the surface of the semiconductor substrate in the trenches. Further, the method includes forming a second stress layer containing carbon atoms with a surface leveling with or higher than the surface of the semiconductor substrate on the first stress layer; and forming a source region and a drain region in the semiconductor substrate at both sides of the first gate structure.

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate having a first region; and forming a first gate structure on a surface of the semiconductor substrate in the first region. The method also includes forming trenches in the semiconductor substrate at both sides of the first gate structure; and forming a first stress layer with one surface lower than the surface of the semiconductor substrate in the trenches. Further, the method includes forming a second stress layer containing carbon atoms with a surface leveling with or higher than the surface of the semiconductor substrate on the first stress layer; and forming a source region and a drain region in the semiconductor substrate at both sides of the first gate structure.

Abstract: The disclosure involves a semiconductor device and a manufacturing method thereof. First, a dielectric layer and a stack comprising a Si layer and at least one SiGe layer located on the Si layer are formed in sequence on a substrate. Then the stack and the dielectric layer are patterned to form a dummy gate and a gate dielectric layer, respectively. Next, sidewall spacers are formed on opposite sides of the dummy gate, and source and drain regions with embedded SiGe are formed. Then, the dummy gate is removed to form an opening, in which a gate material such as metal is filled. In RMG techniques, by adopting the stack consisting of Si and SiGe layers as a dummy gate, the method can further increase the compressive stress in the channel of a MOS device and thus improve carrier mobility as compared to traditional polysilicon dummy gate process.

Abstract: Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer can be formed on the source and the drain. The second sidewall can be removed to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer. A stress layer can be formed on the exposed surface portion of the semiconductor substrate, on the metal silicide layer, on the first sidewall, and on the gate.

Abstract: A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer.

Abstract: This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.

Abstract: A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.

Abstract: This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.

Abstract: A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a ? shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.

Abstract: A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.

Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into ? form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a ?-shaped recess with a cuspate bottom.

Abstract: A method for manufacturing a semiconductor device comprises: forming a recess in a substrate; implanting at the bottom of the recess to form an amorphous layer to a predetermined depth under the bottom of the recess; carrying out crystal orientation selective wet etching to form a Sigma shaped recess by use of the amorphous layer as a stopping layer. Through forming an amorphous layer by means of implantation which is used as a stopping layer in a subsequent wet etching, a Sigma shaped recess with a cuspate bottom is avoided, and a Sigma shaped recess having a planar bottom is obtained, which may further improve semiconductor device performance.