Patents by Inventor Yonghao Xiu
Yonghao Xiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10115606Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.Type: GrantFiled: April 26, 2016Date of Patent: October 30, 2018Assignee: Intel CorporationInventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
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Publication number: 20180286704Abstract: A process for applying an underfill material to a die is disclosed. A wafer is diced into a plurality of dies (without having any underfill film thereon) such that the dies have exposed bumps prior to an underfill process. Thus, the dies can be tested about their bump-sides because the bumps are entirely exposed for testing. The dies are then reconstituted bump-side up on a carrier panel in an array such that the dies are separated from each other by a gap. Underfill material (e.g., epoxy flux film) is then vacuum laminated to the carrier panel and the plurality of dies to encapsulate the dies. The underfill material is then cut between adjacent dies such that a portion of the underfill material covers at least one side edge of each die. The encapsulated dies are then removed from the carrier panel, thereby being prepared for a thermal bonding process to a substrate. Associated devices are provided.Type: ApplicationFiled: April 1, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Elizabeth M. Nofen, Arjun Krishnan, James C. Matayabas, JR., Venmathy McMahan, Nisha Ananthakrishnan, Yonghao Xiu
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Patent number: 9611372Abstract: An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.Type: GrantFiled: February 19, 2016Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Yonghao Xiu, Nisha Ananthakrishnan, Yiqun Bai, Arjun Krishnan
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Publication number: 20160343591Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 1, 2016Publication date: November 24, 2016Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen-Givoni, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
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Patent number: 9431274Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.Type: GrantFiled: December 20, 2012Date of Patent: August 30, 2016Assignee: Intel CorporationInventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
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Publication number: 20160240395Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.Type: ApplicationFiled: April 26, 2016Publication date: August 18, 2016Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
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Publication number: 20160168351Abstract: An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.Type: ApplicationFiled: February 19, 2016Publication date: June 16, 2016Inventors: Yonghao Xiu, Nisha Ananthakrishnan, Yiqun Bai, Arjun Krishnan
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Patent number: 9330993Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.Type: GrantFiled: December 20, 2012Date of Patent: May 3, 2016Assignee: Intel CorporationInventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
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Patent number: 9269596Abstract: An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.Type: GrantFiled: December 19, 2013Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Yonghao Xiu, Nisha Ananthakrishnan, Yiqun Bai, Arjun Krishnan
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Patent number: 9230833Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.Type: GrantFiled: March 4, 2015Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Manish Dubey, Rajendra C. Dias, Yonghao Xiu, Arjun Krishnan, Yiqun Bai, Purushotham Kaushik Muthur Srinath
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Publication number: 20150179478Abstract: An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Inventors: Yonghao Xiu, Nisha Ananthakrishnan, Yiqun Bai, Arjun Krishnan
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Publication number: 20150179479Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.Type: ApplicationFiled: March 4, 2015Publication date: June 25, 2015Applicant: INTEL CORPORATIONInventors: Manish Dubey, Rajendra C. Dias, Yonghao Xiu, Arjun Krishnan, Yiqun Bai, Purushothan Kaushik Muthur Srinath
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Patent number: 8999765Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.Type: GrantFiled: June 25, 2013Date of Patent: April 7, 2015Assignee: Intel CorporationInventors: Manish Dubey, Rajendra C. Dias, Yonghao Xiu, Arjun Krishnan, Yiqun Bai, Purushotham Kaushik Muthur Srinath
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Publication number: 20140377916Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Manish Dubey, Rajendra C. Dias, Yonghao Xiu, Arjun Krishnan, Yiqun Bai, Purushotham Kaushik Muthur Srinath
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Patent number: 8916981Abstract: Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality of conductive contacts couples the surface of the semiconductor die to the surface of the semiconductor package substrate. An epoxy-amine underfill material is disposed between the surface of the semiconductor die and the surface of the semiconductor package substrate and surrounds the plurality of conductive contacts. The epoxy-amine underfill has high adhesion and is based on a low volatility multi-functional amine species.Type: GrantFiled: May 10, 2013Date of Patent: December 23, 2014Assignee: Intel CorporationInventors: Yonghao Xiu, Yiqun Bai, Nisha Ananthakrishnan, Nachiket R. Raravikar
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Publication number: 20140332966Abstract: Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality of conductive contacts couples the surface of the semiconductor die to the surface of the semiconductor package substrate. An epoxy-amine underfill material is disposed between the surface of the semiconductor die and the surface of the semiconductor package substrate and surrounds the plurality of conductive contacts. The epoxy-amine underfill has high adhesion and is based on a low volatility multi-functional amine species.Type: ApplicationFiled: May 10, 2013Publication date: November 13, 2014Inventors: Yonghao Xiu, Yiqun Bai, Nisha Ananthakrishnan, Nachiket R. Raravikar
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Publication number: 20140175634Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
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Publication number: 20140177149Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
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Patent number: 8278191Abstract: Disclosed herein are various embodiments related to metal-assisted chemical etching of substrates on the micron, sub-micron and nano scales. In one embodiment, among others, a method for metal-assisted chemical etching includes providing a substrate; depositing a non-spherical metal catalyst on a surface of the substrate; etching the substrate by exposing the non-spherical metal catalyst and the substrate to an etchant solution including a composition of a fluoride etchant and an oxidizing agent; and removing the etched substrate from the etchant solution.Type: GrantFiled: March 31, 2010Date of Patent: October 2, 2012Assignee: Georgia Tech Research CorporationInventors: Owen Hildreth, Ching Ping Wong, Yonghao Xiu
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Publication number: 20100248449Abstract: Disclosed herein are various embodiments related to metal-assisted chemical etching of substrates on the micron, sub-micron and nano scales. In one embodiment, among others, a method for metal-assisted chemical etching includes providing a substrate; depositing a non-spherical metal catalyst on a surface of the substrate; etching the substrate by exposing the non-spherical metal catalyst and the substrate to an etchant solution including a composition of a fluoride etchant and an oxidizing agent; and removing the etched substrate from the etchant solution.Type: ApplicationFiled: March 31, 2010Publication date: September 30, 2010Applicant: GEORGIA TECH RESEARCH CORPORATIONInventors: Owen Hildreth, C. P. Wong, Yonghao Xiu