Patents by Inventor YongHee Kang

YongHee Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220165857
    Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.
    Type: Application
    Filed: June 21, 2021
    Publication date: May 26, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yonghee PARK, Myunggil KANG, Uihui KWON, Seungkyu KIM, Ahyoung KIM, Youngseok SONG
  • Publication number: 20220056334
    Abstract: A curable composition, a cured layer manufactured utilizing the same, and a display device including the cured layer are provided. The curable composition includes (A) a quantum dot; and (B) a polymerizable compound, wherein the polymerizable compound is a compound represented by Chemical Formula 1. In Chemical Formula 1, each substituent is the same as defined in the specification.
    Type: Application
    Filed: August 10, 2021
    Publication date: February 24, 2022
    Inventors: Injae LEE, Yonghee KANG, Jonggi KIM, Minjee PARK, Dongjun KIM, Bumjin LEE, Minkyeol CHUNG
  • Publication number: 20220052421
    Abstract: The present invention relates to a porous separator comprising a porous layer containing a plurality of plate-type inorganic particles and a first binder polymer positioned on part or all of the surface of the plate-type inorganic particles to connect and fix between the plate-type inorganic particles; and a metal layer formed on any one surface of the porous layer, and a lithium secondary battery comprising the same.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 17, 2022
    Applicant: LG CHEM, LTD.
    Inventors: Woongchul CHOI, Junghun CHOI, Yonghee KANG, Minchul JANG, Suk Il YOUN, Byoungkuk SON
  • Publication number: 20210108135
    Abstract: Quantum dots surface-modified with a compound represented by Chemical Formula 1 or Chemical Formula 2, a curable composition including the quantum dots, a cured layer, and a color filter. In Chemical Formula 1 and Chemical Formula 2, each substituent is the same as defined in the specification.
    Type: Application
    Filed: September 22, 2020
    Publication date: April 15, 2021
    Inventors: Yonghee KANG, Jonggi KIM, Jihyeon YIM, Dongjun KIM, Misun KIM, Minjee PARK, Bumjin LEE, Injae LEE, Mi Jeong CHOI
  • Patent number: 10915020
    Abstract: A photosensitive resin composition including (A) a quantum dot; (B) a binder resin including a structural unit represented by Chemical Formula 1; (C) a photopolymerizable monomer; (D) a photopolymerization initiator; and (E) a solvent, photosensitive resin layer manufactured using the same, and a color filter including the photosensitive resin layer. (In Chemical Formula 1, each substituent is the same as defined in the specification.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 9, 2021
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jiyoung Jeong, Bumjin Lee, Yonghee Kang, Misun Kim, Jonggi Kim, Onyou Park, Hojeong Paek, Byeonggeun Son, Youn Je Ryu, Jinsuop Youn, Jihyeon Yim, Young Woong Jang, Minkyeol Chung, Hyunjoo Han, Kyunghee Hyung
  • Publication number: 20210024819
    Abstract: A quantum dot surface-modified with a specific compound, a non-solvent curable composition including the quantum dot, a solvent based curable composition including the quantum dot, a cured layer manufactured utilizing the curable composition, a color filter including the cured layer, and a display device including the cured layer are disclosed.
    Type: Application
    Filed: January 14, 2020
    Publication date: January 28, 2021
    Inventors: Yonghee KANG, Jonggi KIM, Dongjun KIM, Misun KIM, Minjee PARK, Bumjin LEE, Jihyeon YIM, Mi Jeong CHOI
  • Publication number: 20200248068
    Abstract: A non-solvent curable composition including a quantum dot and a polymerizable monomer having a carbon-carbon double bond at the terminal end and having a vapor pressure of about 1×10?5 mmHg to about 1×10?4 mmHg, a cured layer manufactured utilizing the non-solvent curable composition, a color filter including the cured layer, a display device including the color filter, and a method of manufacturing the cured layer are disclosed.
    Type: Application
    Filed: January 14, 2020
    Publication date: August 6, 2020
    Inventors: Mi Jeong CHOI, Yonghee KANG, Dongjun KIM, Misun KIM, Jonggi KIM, Minjee PARK, Bumjin LEE, Jihyeon YIM
  • Publication number: 20200231871
    Abstract: A quantum dot surface-modified with a ligand, a non-solvent curable composition including the quantum dot, a solvent-based curable composition including the quantum dot, a cured layer manufactured utilizing the curable composition, a color filter including the cured layer, a display device including the color filter, and a method of manufacturing the cured layer are disclosed.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 23, 2020
    Inventors: Jonggi KIM, Yonghee KANG, Dongjun KIM, Misun KIM, Minjee PARK, Bumjin LEE, Jihyeon YIM, Mi Jeong CHOI
  • Publication number: 20190278177
    Abstract: A photosensitive resin composition including (A) a quantum dot; (B) a binder resin including a structural unit represented by Chemical Formula 1; (C) a photopolymerizable monomer; (D) a photopolymerization initiator; and (E) a solvent, photosensitive resin layer manufactured using the same, and a color filter including the photosensitive resin layer. (In Chemical Formula 1, each substituent is the same as defined in the specification.
    Type: Application
    Filed: November 28, 2017
    Publication date: September 12, 2019
    Inventors: Jiyoung JEONG, Bumjin LEE, Yonghee KANG, Misun KIM, Jonggi KIM, Onyou PARK, Hojeong PAEK, Byeonggeun SON, Youn Je RYU, Jinsuop YOUN, Jihyeon YIM, Young Woong JANG, Minkyeol CHUNG, Hyunjoo HAN, Kyunghee HYUNG
  • Publication number: 20190129302
    Abstract: A photosensitive resin composition includes: (A) a binder resin; (B) a photopolymerizable monomer; (C) a photopolymerization initiator; (D) a quantum dot surface-modified with a compound having a thiol group at one terminal end and an alkoxy group, a cycloalkyl group, a carboxyl group, or a hydroxy group at the other terminal end; and (E) a solvent. A curable composition includes: (A?) a resin; (B?) a quantum dot surface-modified with a compound represented by Chemical Formula 1 or Chemical Formula 2; and (C?) a solvent. A method of manufacturing the surface-modified quantum dot, and a color filter manufactured using the photosensitive resin composition or the curable composition are also disclosed.
    Type: Application
    Filed: October 9, 2018
    Publication date: May 2, 2019
    Inventors: Jinsuop YOUN, Misun KIM, Hong Jeong YU, Bumjin LEE, Yonghee KANG, Dongjun KIM, Byeonggeun SON, Jihyeon YIM, Mi Jeong CHOI, Jonggi KIM, Minjee PARK, Hojeong PAEK, Woo Jung SHIN, Young Woong JANG
  • Patent number: 9524958
    Abstract: A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: December 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JoonYoung Choi, YongHee Kang, HunTeak Lee, KeonTaek Kang, YoungChul Kim
  • Patent number: 8994048
    Abstract: A semiconductor device has a substrate with a first and second recess formed in a surface of the substrate using a wet etch process. The second recess can have a size different from a size of the first recess. A plurality of conductive vias are formed in a surface of the first and second recesses using a dry etch process. A first conductive layer is formed over the surface of the substrate, over curved side walls of the first and second recesses, and electrically connected to the plurality of conductive vias. A first and second semiconductor die are mounted into the first and second recesses respectively. The second semiconductor die can have a size different from a size of the first semiconductor die. The first and second semiconductor die are electrically connected to the first conductive layer. An interconnect structure is electrically connected to the plurality of conductive vias.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JoonYoung Choi, YongHee Kang
  • Publication number: 20150001703
    Abstract: A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: JoonYoung Choi, YongHee Kang, HunTeak Lee, KeonTaek Kang, YoungChul Kim
  • Patent number: 8896133
    Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: November 25, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungWon Cho, KiYoun Jang, YongHee Kang, Hyung Sang Park
  • Patent number: 8786076
    Abstract: A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 22, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: OhHan Kim, YongHee Kang, KyungHoon Lee
  • Patent number: 8742566
    Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: June 3, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KiYoun Jang, SungSoo Kim, YongHee Kang
  • Publication number: 20130234324
    Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.
    Type: Application
    Filed: April 25, 2013
    Publication date: September 12, 2013
    Applicant: STATS ChipPAC, Ltd.
    Inventors: SungWon Cho, KiYoun Jang, YongHee Kang, Hyung Sang Park
  • Patent number: 8492197
    Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungWon Cho, KiYoun Jang, YongHee Kang, Hyung Sang Park
  • Patent number: 8389398
    Abstract: A method of making a semiconductor device comprises providing a carrier, forming a first conductive layer extending above a surface of the carrier, providing a substrate, disposing the first conductive layer into a first surface of the substrate, removing the carrier, forming a second conductive layer extending above the first surface of the substrate to create a vertical offset between the first conductive layer and second conductive layer, and forming a plurality of first bumps over the first conductive layer and second conductive layer. The method further includes the steps of disposing a third conductive layer into a second surface of the substrate opposite the first surface of the substrate, forming a fourth conductive layer extending above the second surface of the substrate to create a vertical offset between the third conductive layer and fourth conductive layer, and forming a plurality of second bumps.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: March 5, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KiYoun Jang, SungSoo Kim, YongHee Kang
  • Publication number: 20120241941
    Abstract: A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 27, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: OhHan Kim, YongHee Kang, KyungHoon Lee