Patents by Inventor Yong-ho Ha

Yong-ho Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128502
    Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.
    Type: Application
    Filed: August 14, 2023
    Publication date: April 18, 2024
    Inventors: Sa Heum Kim, Yong Jun Jang, Yong Gu Kim, Sung Man Cho, Sun Ho Choi, Seong Hyeon Choi, Kyu Sung Park, Young Gyoon Ryu, Suk Gi Hong, Pil Sang Yun, Myeong Ju Ha, Hyun Beom Kim, Hwi Chul Yang
  • Patent number: 11558319
    Abstract: Disclosed is a method of transmitting an instant message. The method includes collecting previous round responses to an instant message transmitted to previous round transmission targets determined from a user group, identifying users who react to the instant message using a chat room by which the instant message is received based on the previous round responses, training a machine learning model that predicts a response of a user as to whether the user is to react to the instant message based on the previous round responses and characteristics of the identified users, determining a current round transmission target from the user group based on the trained machine learning model, and transmitting the instant message to the determined current round transmission target.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 17, 2023
    Assignee: KAKAO CORP.
    Inventors: Yong Ho Ha, Se Hwan Bae
  • Publication number: 20220353214
    Abstract: Disclosed is a method of transmitting an instant message. The method includes collecting previous round responses to an instant message transmitted to previous round transmission targets determined from a user group, identifying users who react to the instant message using a chat room by which the instant message is received based on the previous round responses, training a machine learning model that predicts a response of a user as to whether the user is to react to the instant message based on the previous round responses and characteristics of the identified users, determining a current round transmission target from the user group based on the trained machine learning model, and transmitting the instant message to the determined current round transmission target.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: Yong Ho HA, Se Hwan BAE
  • Patent number: 11127739
    Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun
  • Patent number: 10770560
    Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Hyuk Yim, Kug Hwan Kim, Wan Don Kim, Jung Min Park, Jong Ho Park, Byoung Hoon Lee, Yong Ho Ha, Sang Jin Hyun, Hye Ri Hong
  • Publication number: 20200077056
    Abstract: Shoe capable of projecting images that can be changed, wherein the shoe can not only change images projected in front thereof, so as to attract a wearer's interest, but can also naturally induce his or her walking. The subject matter of the present invention is a shoe capable of projecting images that can be changed, the shoe including a shoe body and an image projector detachably attached to the shoe body so as to project an image onto the ground, wherein the image projector comprises: a light source for emitting light; an image cell installed in front of the light source so as to form an image to be projected; and an image changing means for transmitting a control signal to the image cell so as to change the image to be projected.
    Type: Application
    Filed: November 5, 2019
    Publication date: March 5, 2020
    Inventors: Yong Ho Ha, Hyun Ju Ha
  • Publication number: 20190355825
    Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.
    Type: Application
    Filed: December 10, 2018
    Publication date: November 21, 2019
    Inventors: Jeong Hyuk YIM, Kug Hwan KIM, Wan Don KIM, Jung Min PARK, Jong Ho PARK, Byoung Hoon LEE, Yong Ho HA, Sang Jin HYUN, Hye Ri HONG
  • Patent number: 10438800
    Abstract: Semiconductor devices and methods for fabricating the same are provided. A semiconductor device may include a substrate including first and second regions, a first interface film disposed on the substrate in the first region, a second interface film disposed on the substrate in the second region, a dielectric film disposed on the first and second interface films, a first metal film disposed on the dielectric film in the first region, and a second metal film disposed on the dielectric film in the second region. The first and second interface films may comprise an oxide of the substrate, the first and second metal films may comprise different materials, and the first and second interface films may have different thicknesses. Channels may be provided in the first and second regions, and the channels may be fin-shaped or wire-shaped. The metal films may have different oxygen content.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Tae Hwang, Moon Kyun Song, Nam Gyu Cho, Kyu Min Lee, Soo Jung Choi, Yong Ho Ha, Sang Jin Hyun
  • Publication number: 20180331100
    Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 15, 2018
    Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun
  • Publication number: 20180261460
    Abstract: Semiconductor devices and methods for fabricating the same are provided. A semiconductor device may include a substrate including first and second regions, a first interface film disposed on the substrate in the first region, a second interface film disposed on the substrate in the second region, a dielectric film disposed on the first and second interface films, a first metal film disposed on the dielectric film in the first region, and a second metal film disposed on the dielectric film in the second region. The first and second interface films may comprise an oxide of the substrate, the first and second metal films may comprise different materials, and the first and second interface films may have different thicknesses. Channels may be provided in the first and second regions, and the channels may be fin-shaped or wire-shaped. The metal films may have different oxygen content.
    Type: Application
    Filed: November 29, 2017
    Publication date: September 13, 2018
    Inventors: Yoon Tae HWANG, Moon Kyun SONG, Nam Gyu CHO, Kyu Min LEE, Soo Jung CHOI, Yong Ho HA, Sang Jin HYUN
  • Patent number: 9553094
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wei-Hsiung Tseng, Ju-Youn Kim, Seok-Jun Won, Jong-Ho Lee, Hye-Lan Lee, Yong-Ho Ha
  • Publication number: 20160315087
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Application
    Filed: March 14, 2016
    Publication date: October 27, 2016
    Inventors: Wei-Hsiung TSENG, Ju-Youn KIM, Seok-Jun WON, Jong-Ho LEE, Hye-Lan LEE, Yong-Ho HA
  • Patent number: 9287181
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wei-Hsiung Tseng, Ju-Youn Kim, Seok-Jun Won, Jong-Ho Lee, Hye-Lan Lee, Yong-Ho Ha
  • Publication number: 20150270177
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Application
    Filed: January 8, 2015
    Publication date: September 24, 2015
    Inventors: Wei-Hsiung TSENG, Ju-Youn KIM, Seok-Jun WON, Jong-Ho LEE, Hye-Lan LEE, Yong-Ho HA
  • Publication number: 20140374840
    Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 25, 2014
    Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun
  • Patent number: 8732984
    Abstract: A shock absorbing shoe with a triangle shock absorbing space, the shoe having an outsole and a midsole, wherein the midsole is divided into upper and lower midsoles, a plurality of upper seating holes provided on opposite sides of the upper midsole behind an area corresponding to an arch region of a foot sole, a plurality of lower seating holes provided on opposite sides of the lower midsole. The shoe includes a shock absorbing means having a body member formed longitudinally between the upper and lower midsoles, and wing members provided on opposite sides of the body member. Each wing member includes an upper inclined portion inclined upwards to be received in the associated upper seating hole, a lower inclined portion inclined downwards to be received in the associated lower seating hole, and a connecting portion connecting the upper and lower inclined portions.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: May 27, 2014
    Inventor: Yong-ho Ha
  • Publication number: 20140101972
    Abstract: A shock absorbing shoe with a triangle shock absorbing space, the shoe having an outsole and a midsole, wherein the midsole is divided into upper and lower midsoles, a plurality of upper seating holes provided on opposite sides of the upper midsole behind an area corresponding to an arch region of a foot sole, a plurality of lower seating holes provided on opposite sides of the lower midsole. The shoe includes a shock absorbing means having a body member formed longitudinally between the upper and lower midsoles, and wing members provided on opposite sides of the body member. Each wing member includes an upper inclined portion inclined upwards to be received in the associated upper seating hole, a lower inclined portion inclined downwards to be received in the associated lower seating hole, and a connecting portion connecting the upper and lower inclined portions.
    Type: Application
    Filed: April 24, 2013
    Publication date: April 17, 2014
    Inventor: Yong-ho Ha
  • Publication number: 20130234100
    Abstract: Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.
    Type: Application
    Filed: April 11, 2013
    Publication date: September 12, 2013
    Inventors: Hyeong-Geun An, Dong-Ho Ahn, Young-Soo Lim, Yong-Ho Ha, Jun-Young Jang, Dong-Won Lim, Gyeo-Re Lee, Joon-Sang Park, Han-Bong Ko, Young-Lim Park
  • Patent number: 8513051
    Abstract: Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Ho Ha, Bong-Jin Kuh, Ji-Hye Yi, Jun-Soo Bae
  • Patent number: 8456891
    Abstract: A nonvolatile memory cell includes first and second electrodes and a data storage layer extending between the first and second electrodes. An oxygen diffusion barrier layer is provided, which extends between the data storage layer and the first electrode. An oxygen gettering layer is also provided, which extends between the oxygen diffusion barrier layer and the data storage layer. The oxygen diffusion barrier layer includes aluminum oxide, the oxygen gettering layer includes titanium, the data storage layer includes a metal oxide, such as magnesium oxide, and at least one of the first and second electrodes includes a material selected from a group consisting of tungsten, polysilicon, aluminum, titanium nitride silicide and conductive nitrides.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: June 4, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-gyu Baek, Myung-jong Kim, Yong-ho Ha