Patents by Inventor Yonghui REN

Yonghui REN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11995389
    Abstract: Provided are a connector structure, and a skew calculation method and device. Specifically, the connector structure includes: a first Printed Circuit Board (PCB) (12), which includes a first board (122) and a second board (124), and is connected to a testing device; and a second PCB (14), which includes a third board (142) and a fourth board (144), and is connected to the testing device. The first board (122) is connected to the third board (142) through a connector (16).
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 28, 2024
    Assignee: ZTE CORPORATION
    Inventors: Xinjian Chen, Yonghui Ren, Rongxing Ban, Yingxin Wang
  • Publication number: 20240112667
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for speech synthesis. The methods, systems, and apparatus include actions of obtaining an audio representation of speech of a target speaker, obtaining input text for which speech is to be synthesized in a voice of the target speaker, generating a speaker vector by providing the audio representation to a speaker encoder engine that is trained to distinguish speakers from one another, generating an audio representation of the input text spoken in the voice of the target speaker by providing the input text and the speaker vector to a spectrogram generation engine that is trained using voices of reference speakers to generate audio representations, and providing the audio representation of the input text spoken in the voice of the target speaker for output.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 4, 2024
    Applicant: Google LLC
    Inventors: Ye Jia, Zhifeng Chen, Yonghui Wu, Jonathan Shen, Ruoming Pang, Ron J. Weiss, Ignacio Lopez Moreno, Fei Ren, Yu Zhang, Quan Wang, Patrick An Phu Nguyen
  • Publication number: 20230400635
    Abstract: Provided are a method for determining parameters of a waveguide core in an optical-electronic printed circuit board, an optical-electronic printed circuit board, an electronic device, and a storage medium. The method includes: determining, according to a refractive index of a material from which the waveguide core is made and a refractive index of a material from which a base layer is made, a critical angle of total reflection at an interface between the waveguide core and the base layer; and determining the parameters of the waveguide core according to a relative positional relationship between one end port of the waveguide core and the other end port of the waveguide core in the optical-electronic printed circuit board, a condition of a region through which the waveguide core passes, and the critical angle, so that steering of the waveguide core is achieved without introducing a curved surface to the waveguide core.
    Type: Application
    Filed: October 27, 2021
    Publication date: December 14, 2023
    Inventors: Xiaolin CHEN, Hao TIAN, Yonghui REN, Bi YI
  • Publication number: 20230284375
    Abstract: The present application relates to a circuit technology, and discloses a printed circuit board, including: a board body portion comprising a plurality of core boards and a plurality of dielectric layers, the plurality of core boards including a plurality of conductor layers, and the plurality of conductor layers including a differential signal transmission layer located on a surface layer of the board body portion and a differential signal line out layer located on an inner layer of the board body portion; two opposite differential signal holes located on the board body portion, the two differential signal holes being passed sequentially from the differential signal transmission layer to the differential signal line out layer through at least a portion of the core boards and connect the differential signal transmission layer to the differential signal line out layer; and two slotted conductive posts located between the two differential signal holes.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Inventors: Changgang YIN, Zhongmin Wei, Bi Yi, Yonghui Ren
  • Publication number: 20220100945
    Abstract: Provided are a connector structure, and a skew calculation method and device. Specifically, the connector structure includes: a first Printed Circuit Board (PCB) (12), which includes a first board (122) and a second board (124), and is connected to a testing device; and a second PCB (14), which includes a third board (142) and a fourth board (144), and is connected to the testing device. The first board (122) is connected to the third board (142) through a connector (16).
    Type: Application
    Filed: October 14, 2019
    Publication date: March 31, 2022
    Inventors: Xinjian CHEN, Yonghui REN, Rongxing BAN, Yingxin WANG
  • Patent number: 10064271
    Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 28, 2018
    Assignee: ZTE CORPORATION
    Inventors: Bi Yi, Fengchao Ma, Yonghui Ren, Wang Xiong, Yingxin Wang
  • Publication number: 20160323995
    Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 3, 2016
    Inventors: Bi YI, Fengchao MA, Yonghui REN, Wang XIONG, Yingxin WANG