Abstract: An example apparatus includes: a bus connection including a common terminal; a first data terminal; and a second data terminal; an amplifier having an input terminal and an output terminal, the input terminal of the amplifier coupled to the common terminal; charge pump circuitry having an input terminal, a first output terminal, and a second output terminal, the input terminal of the charge pump circuitry coupled to the output terminal of the amplifier; receiver circuitry having an input terminal, a first supply terminal, and a second supply terminal, the input terminal of the receiver circuitry coupled to the first data terminal; and transmitter circuitry having an output terminal, a first supply terminal, and a second supply terminal, the output terminal of the transmitter circuitry coupled to the second data terminal, the first supply terminal of the transmitter circuitry coupled to the first output terminal of the charge pump circuitry.

Abstract: In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.

Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

Abstract: In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.

Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

Abstract: In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.

Abstract: An example apparatus includes: a first input and a second input, a first equalizer with a third input, a fourth input, and a fifth input, the third input coupled to the first input, the fourth input coupled to the second input, a second equalizer with a sixth input, a seventh input, and an eighth input, the sixth input coupled to the first input, the seventh input coupled to the second input, and a controller coupled to the fifth input and the eighth input.

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.

Abstract: In one embodiment, a current source is coupled to a channel input of a switch, and an output of the switch is coupled to a positive or negative data line in a USB 2.0 communication system. In addition, a first input of the voltage threshold comparator is coupled to the negative data line, a second input of the voltage threshold comparator is coupled to a positive data line, and an output of the voltage threshold comparator is coupled to a control input of the switch.

Abstract: A jitter compensation circuit operates in a first conduction state responsive to a high-to low transition of data and a low-to-high transition of data. The circuit operates in a second conduction state when there is no transition of data. The circuit compensates charge to a voltage supply in the first conduction state, thereby reducing voltage drop caused by transition of data.

Abstract: In one embodiment, a current source is coupled to a channel input of a switch, and an output of the switch is coupled to a positive or negative data line in a USB 2.0 communication system. In addition, a first input of the voltage threshold comparator is coupled to the negative data line, a second input of the voltage threshold comparator is coupled to a positive data line, and an output of the voltage threshold comparator is coupled to a control input of the switch.

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.

Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.

Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.