Patents by Inventor YONGHUI YANG

YONGHUI YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240127791
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating speech from text. One of the systems includes one or more computers and one or more storage devices storing instructions that when executed by one or more computers cause the one or more computers to implement: a sequence-to-sequence recurrent neural network configured to: receive a sequence of characters in a particular natural language, and process the sequence of characters to generate a spectrogram of a verbal utterance of the sequence of characters in the particular natural language; and a subsystem configured to: receive the sequence of characters in the particular natural language, and provide the sequence of characters as input to the sequence-to-sequence recurrent neural network to obtain as output the spectrogram of the verbal utterance of the sequence of characters in the particular natural language.
    Type: Application
    Filed: November 21, 2023
    Publication date: April 18, 2024
    Inventors: Samuel Bengio, Yuxuan Wang, Zongheng Yang, Zhifeng Chen, Yonghui Wu, Ioannis Agiomyrgiannakis, Ron J. Weiss, Navdeep Jaitly, Ryan M. Rifkin, Robert Andrew James Clark, Quoc V. Le, Russell J. Ryan, Ying Xiao
  • Publication number: 20240125969
    Abstract: The present disclosure provides a method for experimentally determining a critical sand-carrying gas velocity of a shale gas well. The method includes: collecting well structure and production data, calculating parameter ranges of a gas flow velocity and a liquid flow velocity; carrying out a physical simulation experiment of sand carrying in the shale gas well to obtain the sand holding capacity of the wellbore under different experimental conditions, and calculating a sand holding rate; by observing a change curve of the sand holding rate of the wellbore vs. the gas flow velocity, defining a turning point, and sensitively analyzing the influence of other experimental variables on the turning point, to calculate the critical sand-carrying production of the shale gas well under different conditions. Therefore, this calculation method is simple and applicable, and provides a theoretical basis for the optimization design of water drainage and gas production process.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 18, 2024
    Applicant: Southwest Petroleum University
    Inventors: Yonghui Liu, Jinhong Jiang, Chengcheng Luo, Ning Wu, Xuanzhi Zheng, Xinke Tang, Xin Li, Zhengyang Liu, Boren Yang, Tianjian Liu
  • Publication number: 20240084972
    Abstract: A CO2 gas-liquid phase transition-based multistage compression energy storage apparatus for converting thermal energy into mechanical energy, including: a gas storage; a liquid storage tank; an energy storage assembly, which includes compressors and energy storage heat exchangers; an energy release assembly (400), which includes energy release heat exchangers and expanders; a heat exchange assembly the energy generated by the energy storage assembly, and the energy release heat exchangers being capable of receiving the energy temporarily stored by the heat exchange assembly; and a driving assembly, which includes an energy input member and a first driving member, the energy input member absorbing external thermal energy to drive the first driving member to work, and the first driving member being used for driving the compressors to work.
    Type: Application
    Filed: December 8, 2021
    Publication date: March 14, 2024
    Inventors: Yonghui XIE, Qin WANG, Lei SUN, Yuqi WANG, Di ZHANG, Yongliang GUO, Xiaoyong WANG, Feng YANG
  • Publication number: 20240038853
    Abstract: The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.
    Type: Application
    Filed: April 26, 2021
    Publication date: February 1, 2024
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou TAN, Tian XIAO, Jiahao ZHANG, Yonghui YANG, Xiaoquan LI, Pengfei WANG, Ying PEI, Guangbo LI, Hequan JIANG, Peijian ZHANG, Sheng QIU, Liang CHEN, Wei CUI
  • Publication number: 20230411464
    Abstract: A shared-dielectric MOSFET device with a resistive-field-plate and a preparation method are provided. In the shared-dielectric MOSFET device, the semi-insulating resistive-field-plate electrically connected to the trench gate structure and the drain structure is introduced in the drift region of the existing trench gate MOS devices, and when the trench gate structure controls the MOS channel to be turned on or turned off, the semi-insulating resistive-field-plate can adjust the doping concentration of the drift region, to modulate the conductance of the on-state drift region and the distribution of a off-state high-voltage blocking electric field, thereby obtaining a lower on-resistance. Meanwhile, in the preparation method of the present disclosure, the modern 2.
    Type: Application
    Filed: November 1, 2021
    Publication date: December 21, 2023
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou TAN, Tian XIAO, Jiahao ZHANG, Xiaoquan LI, Pengfei WANG, Ying PEI, Guangbo LI, Yonghui YANG, Hequan JIANG, Peijian ZHANG, Sheng QIU, Liang CHEN, Wei CUI
  • Patent number: 10483358
    Abstract: A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 19, 2019
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou Tan, Gangyi Hu, Zhaohuan Tang, Jianan Wang, Yonghui Yang, Yi Zhong, Yang Cao, Yong Liu, Kunfeng Zhu
  • Publication number: 20190027563
    Abstract: A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 24, 2019
    Applicant: No. 24 Research Institute of China Electronics Technology Group Corporation
    Inventors: KAIZHOU TAN, GANGYI HU, ZHAOHUAN TANG, JIANAN WANG, YONGHUI YANG, YI ZHONG, YANG CAO, YONG LIU, KUNFENG ZHU