Patents by Inventor Yong Hwan Kwon

Yong Hwan Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260040865
    Abstract: Disclosed is a high-pressure annealing device including a nozzle assembly. The high-pressure annealing device is configured to prevent, when gas is supplied to the inside of a chamber of the high-pressure annealing device through a gas nozzle, damage generated during coupling of the gas nozzle to a gas supply module.
    Type: Application
    Filed: June 17, 2025
    Publication date: February 5, 2026
    Applicant: YEST Co., Ltd.
    Inventors: Young Joon HAM, Jeong Eui KIM, Yong Hwan KWON, Jin Seok LEE, Byung Wook HWANG, Yeon Min MO, Eun Chan LEE, Ryun Hwi KIM
  • Patent number: 12538815
    Abstract: A semiconductor package is provided and includes: a base substrate; an interposer package on the base substrate; and first and second semiconductor chips on the interposer package, wherein the interposer package includes: a first redistribution structure including a first insulating layer, a second insulating layer on the first insulating layer, and first and second redistribution layers respectively disposed on the first and second insulating layers; a bridge chip on a bottom surface of the first redistribution structure; a connection structure on the bottom surface of the first redistribution structure and including a plurality of wiring layers electrically connected to the first and second semiconductor chips; and a bonding structure disposed on a third insulating layer on the second insulating layer and bonding each of the first and second semiconductor chips to the first redistribution structure, wherein the second redistribution layer includes a contact plug within the third insulating layer.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: January 27, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yong Hwan Kwon
  • Publication number: 20260016228
    Abstract: Disclosed is a high-pressure annealing device including an internal chamber configured to provide an internal space, an external chamber configured to accommodate the internal chamber therein, a heating module configured to perform heat treatment and disposed in an external space provided between the internal chamber and the external chamber, and a shielding element configured to seal the lower portion of the external space, thereby preventing dispersion of particles generated from the heating module and preventing contamination of a substrate (a semiconductor wafer) due to the particles.
    Type: Application
    Filed: June 30, 2025
    Publication date: January 15, 2026
    Applicant: YEST Co., Ltd.
    Inventors: Young Joon HAM, Jeong Eui KIM, Yong Hwan KWON, Jin Seok LEE, Byung Wook HWANG, Yeon Min MO, Eun Chan LEE, Ryun Hwi KIM
  • Publication number: 20250324487
    Abstract: Disclosed are a jig device for attachment and detachment of a heater unit, a system for attachment and detachment of the heater unit, and a high-pressure annealing device capable of attaching and detaching the heater unit thereto and therefrom. The heater unit is attachable to or detachable from the high-pressure annealing device through upward movement or downward movement of the heater unit from or toward the lower portion of an outer chamber in a state in which the heater unit disposed in the high-pressure annealing device is supported by the jig device.
    Type: Application
    Filed: April 10, 2025
    Publication date: October 16, 2025
    Applicant: YEST Co., Ltd.
    Inventors: Young Joon HAM, Jeong Eui KIM, Yong Hwan KWON, Jin Seok LEE, Byung Wook HWANG, Yeon Min MO, Eun Chan LEE, Ryun Hwi KIM
  • Publication number: 20250234428
    Abstract: A substrate processing apparatus includes a chamber, a chamber door, an outer chamber, and a locking mechanism, in which the chamber door includes a first flange on which a substrate loader or a lower heater accommodating the substrate is placed, a rotating flange rotatably connected to the first flange, and a second flange disposed below the first flange and rotatably connected to the rotating flange.
    Type: Application
    Filed: September 4, 2024
    Publication date: July 17, 2025
    Inventors: Young Joon Ham, Jeong Eui Kim, Yong Hwan Kwon, Jin Seok Lee, Jong Hwan Baek, Byung Wook Hwang, Yeon Min Mo
  • Publication number: 20250198219
    Abstract: A door part used in a semiconductor substrate processing device includes a first flange on which a loader accommodating a wafer is placed, a second flange connected to a lower portion of the first flange, a caught protrusion part extending downward from an edge of the first flange, a door disposed below the second flange, and a guide connected to an upper surface of the door and in which a groove corresponding to a shape of at least a portion of the caught protrusion part is formed so that the caught protrusion part sits on the groove, in which the caught protrusion part is unseated from the groove of the guide depending on a height between the first flange and the door, and the door is rotatable when the caught protrusion part is unseated from the groove.
    Type: Application
    Filed: September 4, 2024
    Publication date: June 19, 2025
    Inventors: Young Joon Ham, Jeong Eui Kim, Yong Hwan Kwon, Jin Seok Lee, Jong Hwan Baek
  • Publication number: 20250191942
    Abstract: A substrate processing apparatus includes a chamber, a chamber door configured to open or close a chamber opening, an outer chamber configured to surround the chamber, in which the outer chamber includes an outer chamber upper surface, an outer chamber side surface, and an outer chamber base on an opposite side of the outer chamber upper surface and configured to seal between a chamber side surface and the outer chamber side surface, in which the outer chamber upper surface, the outer chamber side surface, and the outer chamber base form a sealed space between the outer chamber and the chamber.
    Type: Application
    Filed: September 4, 2024
    Publication date: June 12, 2025
    Inventors: Young Joon Ham, Jeong Eui Kim, Yong Hwan Kwon, Jin Seok Lee, Jong Hwan Baek, Byung Wook Hwang, Yeon Min Mo
  • Publication number: 20240014139
    Abstract: A semiconductor package is provided and includes: a base substrate; an interposer package on the base substrate; and first and second semiconductor chips on the interposer package, wherein the interposer package includes: a first redistribution structure including a first insulating layer, a second insulating layer on the first insulating layer, and first and second redistribution layers respectively disposed on the first and second insulating layers; a bridge chip on a bottom surface of the first redistribution structure; a connection structure on the bottom surface of the first redistribution structure and including a plurality of wiring layers electrically connected to the first and second semiconductor chips; and a bonding structure disposed on a third insulating layer on the second insulating layer and bonding each of the first and second semiconductor chips to the first redistribution structure, wherein the second redistribution layer includes a contact plug within the third insulating layer.
    Type: Application
    Filed: April 24, 2023
    Publication date: January 11, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yong Hwan KWON
  • Patent number: 11634996
    Abstract: An apparatus for controlling tip clearance between a turbine casing and a turbine blade is provided. The apparatus for controlling tip clearance includes a casing surrounding the turbine blade, a cooling plate installed in a groove and formed in a circumferential direction in the casing, the cooling plate being contracted by cold air supplied thereto, an upper plate mounted radially outside the cooling plate in the groove and having a plurality of cold air holes formed therein, a cylinder extending radially from an inner peripheral surface of the upper plate and having a plurality of cooling holes formed on a side thereof, and a ring segment mounted radially inside the cooling plate.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: April 25, 2023
    Assignee: DOOSAN ENERBILITY CO., LTD.
    Inventors: Seung Min Lee, Yong Hwan Kwon, Dong Il Kim, Jin Woong Ha
  • Patent number: 11371378
    Abstract: An apparatus for controlling tip clearance between a turbine casing and a turbine blade is provided. The apparatus for controlling tip clearance includes a casing surrounding the turbine blade, a cooling plate installed in a groove, formed in a circumferential direction in the casing, and contracted by cold air supplied thereto, the cooling plate having at least one fin formed on an outer peripheral surface thereof, and a ring segment mounted radially inside the cooling plate.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 28, 2022
    Inventors: Seung Min Lee, Yong Hwan Kwon, Dong II Kim, Jin Woong Ha
  • Patent number: 11244921
    Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Eun Joo, Sung Hoan Kim, Kyung Moon Jung, Yong Hwan Kwon, Young Kyu Lim, Seong Hwan Park
  • Publication number: 20210348519
    Abstract: An apparatus for controlling tip clearance between a turbine casing and a turbine blade is provided. The apparatus for controlling tip clearance includes a casing surrounding the turbine blade, a cooling plate installed in a groove, formed in a circumferential direction in the casing, and contracted by cold air supplied thereto, the cooling plate having at least one fin formed on an outer peripheral surface thereof, and a ring segment mounted radially inside the cooling plate.
    Type: Application
    Filed: March 18, 2021
    Publication date: November 11, 2021
    Inventors: Seung Min LEE, Yong Hwan KWON, Dong II KIM, Jin Woong HA
  • Publication number: 20210301674
    Abstract: An apparatus for controlling tip clearance between a turbine casing and a turbine blade is provided. The apparatus for controlling tip clearance includes a casing surrounding the turbine blade, a cooling plate installed in a groove and formed in a circumferential direction in the casing, the cooling plate being contracted by cold air supplied thereto, an upper plate mounted radially outside the cooling plate in the groove and having a plurality of cold air holes formed therein, a cylinder extending radially from an inner peripheral surface of the upper plate and having a plurality of cooling holes formed on a side thereof, and a ring segment mounted radially inside the cooling plate.
    Type: Application
    Filed: March 10, 2021
    Publication date: September 30, 2021
    Inventors: Seung Min Lee, Yong Hwan Kwon, Dong II Kim, Jin Woong Ha
  • Publication number: 20200365545
    Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.
    Type: Application
    Filed: December 20, 2019
    Publication date: November 19, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Eun JOO, Sung Hoan KIM, Kyung Moon JUNG, Yong Hwan KWON, Young Kyu LIM, Seong Hwan PARK
  • Patent number: 10268004
    Abstract: Provided herein are a multi-channel receiver optical sub-assembly and a manufacturing method thereof. The multi-channel receiver optical sub-assembly includes a PLC chip having a first side into which an optical signal is received and a second side from which the received signal is outputted, with an inclined surface formed on the second side of the PLC chip at a preset angle, a PD carrier bonded onto the PLC chip and made of a glass material, and an SI-PD bonded onto the PD carrier, a lens being integrated therein. The PLC chip, the PD carrier, and the SI-PD are passively aligned by at least one alignment mark and then are bonded.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 23, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Tak Han, Sang Ho Park, Yong Soon Baek, Jang Uk Shin, Yong Hwan Kwon, Jong Hoi Kim
  • Publication number: 20180136419
    Abstract: Provided herein are a multi-channel receiver optical sub-assembly and a manufacturing method thereof. The multi-channel receiver optical sub-assembly includes a PLC chip having a first side into which an optical signal is received and a second side from which the received signal is outputted, with an inclined surface formed on the second side of the PLC chip at a preset angle, a PD carrier bonded onto the PLC chip and made of a glass material, and an SI-PD bonded onto the PD carrier, a lens being integrated therein. The PLC chip, the PD carrier, and the SI-PD are passively aligned by at least one alignment mark and then are bonded.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Tak HAN, Sang Ho PARK, Yong Soon BAEK, Jang Uk SHIN, Yong Hwan KWON, Jong Hoi KIM
  • Patent number: 9904023
    Abstract: Provided herein are a multi-channel receiver optical sub-assembly and a manufacturing method thereof. The multi-channel receiver optical sub-assembly includes a PLC chip having a first side into which an optical signal is received and a second side from which the received signal is outputted, with an inclined surface formed on the second side of the PLC chip at a preset angle, a PD carrier bonded onto the PLC chip and made of a glass material, and an SI-PD bonded onto the PD carrier, a lens being integrated therein. The PLC chip, the PD carrier, and the SI-PD are passively aligned by at least one alignment mark and then are bonded.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: February 27, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Tak Han, Sang Ho Park, Yong Soon Baek, Jang Uk Shin, Yong Hwan Kwon, Jong Hoi Kim
  • Patent number: 9899226
    Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun Ahn, Hae Cheon Kim, Jong Won Lim, Dong Min Kang, Yong Hwan Kwon, Seong Il Kim, Zin Sig Kim, Eun Soo Nam, Byoung Gue Min, Hyung Sup Yoon, Kyung Ho Lee, Jong Min Lee, Kyu Jun Cho
  • Patent number: 9733344
    Abstract: Provided herein a laser radar apparatus including a plurality of light transmission and reception modules arranged concavely in an opposite direction to a scanning direction based on a surface vertical to the scanning direction, wherein each of the plurality of light transmission and reception modules comprises a transmitter configured to deflect a laser beam and to irradiate the deflected laser beam to a target; and a receiver configured to receive the laser beam reflected from the target.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: August 15, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae Sik Sim, Ki Soo Kim, Bong Ki Mheen, Myoung Sook Oh, Hong Seok Seo, Jung Ho Song, Yong Hwan Kwon, Dong Sun Kim, Min Hyup Song, Gyu Dong Choi
  • Patent number: D933688
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kumi Akiyoshi, Melinda Yang, Jimin Kim, Emily Lee, Tony Shumskas, Patrick J. Fiori, Kyle T. McGill, Brian Behnke, Jonathan P. Gaiser, Yuchang Hu, Scott Ysebert, Nikolay Ayrapetov, Eun Sun Mota Choi, Garret Miller, Jorge T. Furuya Mariche, Georgiana Arriola, Yong Hwan Kwon, Mark M. Damico, Kristen Kator