Patents by Inventor Yonghyeok SON

Yonghyeok SON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device including wiring contact plugs
    Patent number: 11901297
    Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 13, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghyeok Son, Junwoo Lee, Sungdong Cho
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING WIRING CONTACT PLUGS
    Publication number: 20230238331
    Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 27, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yonghyeok Son, Junwoo Lee, Sungdong Cho
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING WIRING CONTACT PLUGS
    Publication number: 20230170303
    Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.
    Type: Application
    Filed: January 11, 2023
    Publication date: June 1, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yonghyeok SON, Junwoo LEE, Sungdong CHO
  • Semiconductor memory device including wiring contact plugs
    Patent number: 11569171
    Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 31, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghyeok Son, Junwoo Lee, Sungdong Cho
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING WIRING CONTACT PLUGS
    Publication number: 20220139836
    Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.
    Type: Application
    Filed: May 26, 2021
    Publication date: May 5, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yonghyeok SON, Junwoo LEE, Sungdong CHO