Patents by Inventor Yong Hyuk Choi
Yong Hyuk Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929497Abstract: A negative electrode active material as well as a method of preparing a negative electrode active material which includes preparing a silicon-based compound including SiOx, wherein 0.5<x<1.3; disposing a polymer layer including a polymer compound on the silicon-based compound; disposing a metal catalyst layer on the polymer layer; heat treating the silicon-based compound on which the polymer layer and the metal catalyst layer are disposed; and removing the metal catalyst layer, wherein the polymer compound includes any one selected from the group consisting of glucose, fructose, galactose, maltose, lactose, sucrose, a phenolic resin, a naphthalene resin, a polyvinyl alcohol resin, a urethane resin, polyimide, a furan resin, a cellulose resin, an epoxy resin, a polystyrene resin, a resorcinol-based resin, a phloroglucinol-based resin, a coal-derived pitch, a petroleum-derived pitch, a tar and a mixture of two or more thereof.Type: GrantFiled: November 1, 2019Date of Patent: March 12, 2024Assignee: LG ENERGY SOLUTION, LTD.Inventors: Dong Hyuk Kim, Eun Kyung Kim, Yong Ju Lee, Rae Hwan Jo, Jung Hyun Choi
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Patent number: 11925051Abstract: A display device includes: a first base having a display area; light-emitting elements on the first base; and an encapsulation layer over the light-emitting elements. The encapsulation layer includes: a first inorganic layer; an organic layer on the first inorganic layer; and a second inorganic layer on the organic layer. The first inorganic layer includes: a first buffer layer on the light-emitting elements; a first barrier layer on the first buffer layer; a first porous layer on the first barrier layer; a second barrier layer on the first porous layer; and a second buffer layer on the second barrier layer. A refractive index of the first buffer layer, the first barrier layer, and the first porous layer are different from one another, and the refractive index of the first porous layer is smaller than the refractive index of the first buffer layer and the first barrier layer.Type: GrantFiled: May 7, 2021Date of Patent: March 5, 2024Assignee: Samsung Display Co., Ltd.Inventors: Yong Tack Kim, Eung Seok Park, Jae Hyuk Lee, Yoon Hyeung Cho, Dong Uk Choi
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Patent number: 11170856Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.Type: GrantFiled: December 7, 2020Date of Patent: November 9, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
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Publication number: 20210118512Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Inventors: SANG WAN NAM, YONG HYUK CHOI, JUN YONG PARK, JUNG NO IM
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Patent number: 10964398Abstract: A memory device includes a memory cell region including a metal pad and first and second memory cells in a memory block, a peripheral circuit region including another metal pad and vertically connected to the memory cell region by the metal pads, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region connected to the second memory cell, an address decoder in the peripheral circuit region applying one of an erase voltage and an inhibit voltage to the first and second word lines, and control logic in the peripheral circuit region controlling an erasing operation on the memory block. During the erasing operation the inhibit voltage is applied to the first word line after the erase voltage, and the erase voltage is applied to the second word line after the inhibit voltage.Type: GrantFiled: August 3, 2020Date of Patent: March 30, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
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Patent number: 10892017Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.Type: GrantFiled: July 10, 2019Date of Patent: January 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
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Publication number: 20200365211Abstract: A memory device comprises: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a first memory cell in the memory cell region, and a second memory cell different from the first memory cell in the memory cell region, wherein the first memory cell and the second memory cell are included in a same memory block as each other, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region, different from the first word line, connected to the second memory cell, an address decoder in the peripheral circuit region configured to apply one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines, and a control logic in the peripheral circuit region configured to control an erasing operation on the memory block, using the address decoder, whereinType: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Inventors: SANG WAN NAM, YONG HYUK CHOI, JUN YONG PARK, JUNG NO IM
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Publication number: 20200105347Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.Type: ApplicationFiled: July 10, 2019Publication date: April 2, 2020Inventors: SANG WAN NAM, YONG HYUK CHOI, JUN YONG PARK, JUNG NO IM
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Patent number: 9534801Abstract: A wall mount-type evaporative humidifier according to an embodiment of the present invention includes a main body mounted on a wall and having an air intake port and an air blower port formed therein, a ventilator disposed within the main body and configured to suck air into the air intake port and blow the air toward the air blower port, a water guide disposed within the main body and having a water channel formed therein, a water tank configured to contain water in order to supply the water to the water guide and seated in the water guide, and a humidification filter configured to absorb water of the water guide and to supply moisture to air flowing toward the ventilator and seated in the water guide. The present invention is advantageous in that it can realize a humidifying effect and a cooling effect at the same time, has the high utilization of space, and can control the humidity of the entire room rapidly and uniformly.Type: GrantFiled: December 31, 2008Date of Patent: January 3, 2017Assignee: LG ELECTRONICS INC.Inventors: Yong Hyuk Choi, Chin Hyuk Chang, Dong Wook Kim, Jae Hun Jung, Arunesh Kr Singh, Yo Sang Jung
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Patent number: 8672299Abstract: Disclosed herein is a humidifier. The humidifier includes a rear casing, a front casing placed in front of the rear casing and having an opening formed on its front side, a fan housing having an air intake unit formed on its front side, wherein an air blower unit is formed on one side of a circumference part of the fan housing, a humidification filter placed in front of the air intake unit, and a water tank placed on a side of the humidification filter. The fan housing has a partition wall projected therefrom between the humidification filter and the water tank, and the partition wall partitions a front side of the fan housing into a space through which air passes and a space where the water tank is placed.Type: GrantFiled: December 31, 2008Date of Patent: March 18, 2014Assignee: LG Electronics Inc.Inventors: Yong Hyuk Choi, Yo Sang Jung, Chin Hyuk Chang
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Publication number: 20120064817Abstract: A wall mount-type evaporative humidifier according to an embodiment of the present invention includes a main body mounted on a wall and having an air intake port and an air blower port formed therein, a ventilator disposed within the main body and configured to suck air into the air intake port and blow the air toward the air blower port, a water guide disposed within the main body and having a water channel formed therein, a water tank configured to contain water in order to supply the water to the water guide and seated in the water guide, and a humidification filter configured to absorb water of the water guide and to supply moisture to air flowing toward the ventilator and seated in the water guide. The present invention is advantageous in that it can realize a humidifying effect and a cooling effect at the same time, has the high utilization of space, and can control the humidity of the entire room rapidly and uniformly.Type: ApplicationFiled: December 31, 2008Publication date: March 15, 2012Applicant: LG ELECTRONICS INC.Inventors: Yong Hyuk Choi, Chin Hyuk Chang, Dong Wook Kim, Jae Hun Jung, Arunesh Kr Singh, Yo Sang Jung
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Publication number: 20110291305Abstract: Disclosed herein is a humidifier. The humidifier includes a rear casing, a front casing placed in front of the rear casing and having an opening formed on its front side, a fan housing having an air intake unit formed on its front side, wherein an air blower unit is formed on one side of a circumference part of the fan housing, a humidification filter placed in front of the air intake unit, and a water tank placed on a side of the humidification filter. The fan housing has a partition wall projected therefrom between the humidification filter and the water tank, and the partition wall partitions a front side of the fan housing into a space through which air passes and a space where the water tank is placed.Type: ApplicationFiled: December 31, 2008Publication date: December 1, 2011Applicant: LG ELECTRONICS INCInventors: Yong Hyuk Choi, Yo Sang Jung, Chin Hyuk Chang