Abstract: Various example embodiments are directed to a method, device, and system for repairing a Dynamic Random Access Memory (DRAM) memory device. The method includes reserving a memory space within the DRAM memory device, the reserved memory space including a plurality of spare rows, identifying one or more faulty rows within the DRAM memory device using at least one memory testing method, updating an error information table based on information of a respective classified correctable faulty row, in response to an error count for the respective classified correctable faulty row exceeding a desired threshold value, mapping the respective classified correctable faulty row to an available spare row of the plurality of spare rows, storing the mapping of the respective correctable faulty row and the mapped spare row in a row repair translation table, and copying data stored in the respective correctable faulty row into the mapped spare row.

Abstract: A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot.

Abstract: A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot.