Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

Abstract: Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2x where x ranges from 0 to m?1 and m is a number of single switched capacitors per input line.

Abstract: Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.

Abstract: Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor. The pull-down path includes a diode-connected MOS transistor coupled in parallel with a second MOS transistor that couples the gate terminal of the switching MOS transistor to ground via third and fourth MOS transistors when the switching MOS transistor is in an OFF state. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage, VDD, to activate the pull-down path. A capacitor may be coupled between gate and source terminals of the switching MOS transistor to switch the switching MOS transistor to an ON state.

Abstract: Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.

Abstract: Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

Abstract: Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m?1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADC—fs/128 +VADC—fs/256+VADC—fs/512+VADC—fs/1024 when m equals 4 and where VADC—fs is the full-scale voltage of the ADC.

Abstract: Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.

Abstract: Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m?1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADC—fs/128 +VADC—fs/256+VADC—fs/512+VADC—fs/1024 when m equals 4 and where VADC—fs is the full-scale voltage of the ADC.

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor. The pull-down path includes a diode-connected MOS transistor coupled in parallel with a second MOS transistor that couples the gate terminal of the switching MOS transistor to ground via third and fourth MOS transistors when the switching MOS transistor is in an OFF state. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage, VDD, to activate the pull-down path. A capacitor may be coupled between gate and source terminals of the switching MOS transistor to switch the switching MOS transistor to an ON state.

Abstract: A surface motor direct-drive sucker-rod screw pump device is driven by a vertical three-phase permanent magnet brush-less DC motor, and comprises a motor controller (6), a rectifying circuit, an inversion circuit, a CPU and a driving circuit. The motor controller (6) is used to adjust the voltage and frequency of the motor by the rectifying circuit, the inversion circuit, the CPU and the driving circuit. Thus, the speed of the motor can vary from zero to the maximum. The device is easy to operate and has a higher efficiency.

Abstract: A surface motor direct-drive sucker-rod screw pump device is driven by a vertical three-phase permanent magnet brush-less DC motor, and comprises a motor controller (6), a rectifying circuit, an inversion circuit, a CPU and a driving circuit. The motor controller (6) is used to adjust the voltage and frequency of the motor by the rectifying circuit, the inversion circuit, the CPU and the driving circuit. Thus, the speed of the motor can vary from zero to the maximum. The device is easy to operate and has a higher efficiency.

Abstract: A braking controller of a three-phase permanent magnetic brushless DC motor for directly driving a screw pump includes a detection circuit for detecting power supply states of the three-phase permanent magnetic brushless DC motor and a braking circuit for controlling the braking startup according to the power supply states of the three-phase permanent magnetic brushless DC motor. When the motor is supplied with power, the braking circuit is cut off. When the motor is not supplied with power and the screw pump drives the motor to reverse, the braking circuit starts up.

Abstract: A braking controller of a three-phase permanent magnetic brushless DC motor for directly driving a screw pump includes a detection circuit for detecting power supply states of the three-phase permanent magnetic brushless DC motor and a braking circuit for controlling the braking startup according to the power supply states of the three-phase permanent magnetic brushless DC motor. When the motor is supplied with power, the braking circuit is cut off. When the motor is not supplied with power and the screw pump drives the motor to reverse, the braking circuit starts up.

Abstract: A surface motor direct-drive sucker-rod screw pump device is driven by a vertical three-phase permanent magnet brush-less DC motor, and comprises a motor controller (6), a rectifying circuit, an inversion circuit, a CPU and a driving circuit. The motor controller (6) is used to adjust the voltage and frequency of the motor by the rectifying circuit, the inversion circuit, the CPU and the driving circuit. Thus, the speed of the motor can vary from zero to the maximum. The device is easy to operate and has a higher efficiency.